Chapter 5 Instruction-Set Mapping

The tables in this chapter describe the relationship between hardware instructions of the SPARC architecture, as defined in The SPARC Architecture Manual and the assembly language instruction set recognized by the SunOS 5.x SPARC assembler.

The SPARC-V9 instruction set is described in Appendix E, SPARC-V9 Instruction Set.

5.1 Table Notation

Table 5–1 shows the table notation used in this chapter to describe the instruction set of the assembler. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names.

Table 5–1


Notations	Describes	Comment
`address`	`reg_rs1 + reg_rs2` `reg_rs1 + const13` `reg_rs1 – const13` `const13 + reg_rs1` `const13`	Address formed from register contents, immediate constant, or both.
`asi`		Alternate address space identifier; an unsigned 8–bit value. It can be the result of the evaluation of a symbol expression.
`const13`		A signed constant which fits in 13 bits. It can be the result of the evaluation of a symbol expression.
`const22`		A constant which fits in 22 bits. It can be the result of the evaluation of a symbol expression.
`creg`	`%c0 ... %c31`	Coprocessor registers.
`freg`	`%f0 ... %f31`	Floating-point registers.
`imm7`		A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 ... 127). It can be the result of the evaluation of a symbol expression.
`reg`	`%r0 ... %r31`	General purpose registers.
	`%g0 ... %g7`	Same as `%r0 ... %r7` (Globals)
	`%o0 ... %o7`	Same as `%r8 ... %r15` (Outs)
	`%l0 ... %l7`	Same as `%r16 ... %r23` (Locals)
	`%i0 ... %i7`	Same as `%r24 ... %r31` (Ins)
`reg`_rd		Destination register.
`reg`_rs1`, reg`_rs2		Source register 1, source register 2.
`reg_or_imm`	`reg`_rs2`, const13`	Value from either a single register, or an immediate constant.
`regaddr`	`reg`_rs1 `reg`_rs1 `+ reg`_rs2	Address formed with register contents only.
`Software_trap_number`	`reg_rs1 + reg_rs2` `reg_rs1 + imm7` `reg_rs1 - imm7` `uimm7` `imm7 + reg_rs1`	A value formed from register contents, immediate constant, or both. The resulting value must be in the range 0.....127, inclusive.
`uimm7`		An unsigned constant that can be represented in 7 bits (it is in the range 0 ... 127). It can be the result of the evaluation of a symbol expression.

5.2 Integer Instructions

The notations described in Table 5–2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names).

Table 5–2


Notation	Description
`a`	Instructions that deal with alternate space
`b`	Byte instructions
`c`	Reference to coprocessor registers
`d`	Doubleword instructions
`f`	Reference to floating-point registers
`h`	Halfword instructions
`q`	Quadword instructions
`sr`	Status register

Table 5–3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions.

The syntax of individual instructions is designed so that a destination operand (if any), which may be either a register or a reference to a memory location, is always the last operand in a statement.

Note –

In Table 5–3,

Braces ({ }) indicate optional arguments.

Braces are not literally coded.
Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to.

Brackets are coded literally in the assembly language. Note that the usage of brackets described in Chapter 2, Assembler Syntax differs from the usage of these brackets.
All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ",a" to the opcode mnemonic; for example,

"bgeu,a label"

Table 5–3


Opcode	Mnemonic	Argument List	Operation	Comments
`ADD`	`add`	`reg`_rs1`, reg_or_imm, reg`_rd	Add
`ADDcc`	`addcc`	`reg`_rs1`, reg_or_imm, reg`_rd	Add and modify `icc`
`ADDX`	`addx`	`reg`_rs1`, reg_or_imm, reg`_rd	Add with carry
`ADDXcc`	`addxcc`	`reg`_rs1`, reg_or_imm, reg`_rd
`AND`	`and`	`reg`_rs1, reg_or_imm, reg_rd	And
`ANDcc`	`andcc`	reg_rs1, reg_or_imm, reg_rd
`ANDcc`	`andn`	reg_rs1, reg_or_imm, reg_rd
`ANDNcc`	`andcc`	reg_rs1, reg_or_imm, reg_rd
`BN`	`bn{,a}`	`label`	Branch on integer condition codes	branch never
`BNE`	`bne{,a}`	`label`		synonym: `bnz`
`BE` `BG` `BLE` `BGE` `BI` `BGU` `BLEU`	`be{,a}` `bg{,a}` `ble{,a}` `bge{,a}` `bl{,a}` `bgu{,a}` `bleu{,a}`	`label` `label` `label` `label` `label` `label` `label`		synonym: `bz`
`BCC`	`bcc{,a}`	`label`		synonym: `bgeu`
`BCS` `BPOS` `BNEG` `BVC` `BVS`	`bcs{,a}` `bpos{,a}` `bneg{,a}` `bvc{,a}` `bvs{,a}`	`label` `label` `label` `label` `label`		synonym: `blu`
`BA`	`ba{,a}`	`label`		synonym: `b`
`CALL`	`call`	`label`	Call subprogram
`CBccc`	`cbn{,a}` `cb3{,a}` `cb2{,a}` `cb23{,a}` `cb1{,a}` `cb13{,eo}` `cb12{,a}` `cb123{,a}` `cb0{,a}` `cb03{,a}` `cb02{,a}` `cb023{,a}` `cb01{,a}` `cb013{,a}` `cb012{,a}` `cba{,a}`	`label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label` `label`	Branch on coprocessor condition codes	branch never
`FBN` `FBU` `FBG` `FBUG` `FBL` `FBUL` `FBLG`	`fbn{,a}` `fbu{,a}` `fbg{,a}` `fbug{,a}` `fbl{,a}` `fbul{,a}` `fblg{,a}`	`label` `label` `label` `label` `label` `label` `label`	Branch on floating-point condition codes	branch never
`FBNE`	`fbne{,a}`	`label`		synonym: `fbnz`
`FBE`	`fbe{,a}`	`label`		synonym: `fbz`
`FBUE` `FBGE` `FBUGE` `FBLE` `FBULE` `FBO` `FBA`	`fbue{,a}` `fbge{,a}` `fbuge{,a}` `fble{,a}` `fbule{,a}` `fbo{,a}` `fba{,a}`	`label` `label` `label` `label` `label` `label` `label`
`FLUSH`	`flush`	address	Instruction cache flush
`JMPL`	`jmpl`	address, reg_rd	Jump and link
`LDSB`	`ldsb`	[address], reg_rd	Load signed byte
`LDSH`	`ldsh`	[address], reg_rd	Load signed halfword
`LDSTUB`	`ldstub`	[address], reg_rd	Load-store unsigned byte
`LDUB`	`ldub`	[address], reg_rd	Load unsigned byte
`LDUH`	`lduh`	[address], reg_rd	Load unsigned halfword
`LD`	`ld`	[address], reg_rd	Load word
`LDD`	`ldd`	[address], reg_rd	Load double word	reg_rd must be even
`LDF`	`ld`	[address], freg_rd
`LDFSR`	`ld`	[address], %fsr	Load floating-point register
`LDDF`	`ldd`	[address], freg_rd	Load double floating-point	freg_rd must be even
`LDC`	`ld`	[address], creg_rd	Load coprocessor
`LDCSR`	`ld`	[address], %csr	Load double coprocessor
`LDDC`	`ldd`	[address], creg_rd
`LDSBA` `LDSHA` `LDUBA` `LDUHA` `LDA`	`ldsba` `ldsha` `lduba` `lduha` `lda`	[regaddr]asi, reg_rd [regaddr]asi, reg_rd [regaddr]asi, reg_rd [regaddr]asi, reg_rd [regaddr]asi, reg_rd	Load signed byte from alternate space
`LDDA`	`ldda`	[regaddr]asi, reg_rd		reg_rd must be even
`LDSTUBA`	`ldstuba`	[regaddr]asi, reg_rd
`MULScc`	`mulscc`	reg_rs1, reg_or_imm, reg_rd	Multiply step (and modify `icc`)
`NOP`	`nop`		No operation
`OR` `ORcc` `ORN` `ORNcc`	`or` `orcc` `orn` `orncc`	reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd	Inclusive `or`
`RDASR`	`rd`	`%asrn`_rs1, reg_rd
`RDY`	`rd`	`%y`, reg_rd		See synthetic instructions.
`RDPSR`	`rd`	`%psr`, reg_rd		See synthetic instructions.
`RDWIM`	`rd`	`%wim`, reg_rd		See synthetic instructions.
`RDTBR`	`rd`	`%tbr`, reg_rd		See synthetic instructions.
`RESTORE`	`restore`	reg_rs1, reg_or_imm, reg _rd		See synthetic instructions.
`RETT`	`rett`	address	Return from trap
`SAVE`	`save`	reg_rs1, reg_or_imm, reg_rd		See synthetic instructions.
`SDIV`	`sdiv`	reg_rs1, reg_or_imm, reg_rd	Signed divide
`SDIVcc`	`sdivcc`	reg_rs1, reg_or_imm, reg_rd	Signed divide and modify `icc`
`SMUL`	`smul`	reg_rs1, reg_or_imm, reg_rd	Signed multiply
`SMULcc`	`smulcc`	reg_rs1, reg_or_imm, reg_rd	Signed multiply and modify `icc`
`SETHI`	`sethi`	const22, reg_rd	Set high 22 bits of register
	`sethi`	`%hi`(value), reg_rd		See synthetic instructions.
`SLL`	`sll`	reg_rs1, reg_or_imm, reg_rd	Shift left logical
`SRL`	`srl`	reg_rs1, reg_or_imm, reg_rd	Shift right logical
`SRA`	`sra`	reg_rs1, reg_or_imm, reg_rd	Shift right arithmetic
`STB`	`stb`	reg_rd, [address]	Store byte	Synonyms: `stub`, `stsb`
`STH`	`sth`	reg_rd, [address]	Store half-word	Synonyms: `stuh`, `stsh`
`ST`	`st`	reg_rd, [address]
`STD`	`std`	reg_rd, [address]		reg_rd Must be even
`STF`	`st`	freg_rd, [address]
`STDF`	`std`	freg_rd, [address]
`STFSR`	`st`	`%fsr`, [address]	Store floating-point status register	freg_rd Must be even
`STDFQ`	`std`	`%fq`, [address]	Store double floating-point queue
`STC`	`st`	creg_rd, [address]	Store coprocessor	creg_rd Must be even
`STDC`	`std`	creg_rd, [address]		creg_rd Must be even
`STCSR`	`st`	`%csr`, [address]
`STDCQ`	`std`	`%cq`, [address]	Store double coprocessor
`STBA`	`stba`	reg_rd [regaddr]asi	Store byte into alternate space	Synonyms: stuba, stsba
`STHA`	`stha`	reg_rd [regaddr]asi		Synonyms: stuha, stsha
`STA`	`sta`	reg_rd, [regaddr]asi
`STDA`	`stda`	reg_rd, [regaddr]asi		reg_rd Must be even
`SUB`	`sub`	reg_rs1, reg_or_imm, reg_rd	Subtract
`SUBcc`	`subcc`	reg_rs1, reg_or_imm, reg_rd	Subtract and modify `icc`
`SUBX`	`subx`	reg_rs1, reg_or_imm, reg_rd	Subtract with carry
`SUBXcc`	`subxcc`	reg_rs1, reg_or_imm, reg_rd
`SWAP` `SWAPA`	`swap` `swapa`	[address], reg_rd [regaddr]asi, reg_rd	Swap memory word with register
`Ticc`	`tn`	`software_trap_number`	Trap on integer condition code	Trap never
	`tne`	`software_trap_number`	Note: Trap numbers 16-31 are reserved for the user. Currently-defined trap numbers are those defined in `/usr/include/sys/trap.h`	Synonym: `tnz`
	`te` `tg` `tle` `tge` `tl` `tgu`	`software_trap_number` `software_trap_number` `software_trap_number` `software_trap_number` `software_trap_number` `software_trap_number`		Synonym: `tz`
	`tleu`	`software_trap_number`		Synonym: `tcc`
	`tlu` `tgeu` `tpos` `tneg`	`software_trap_number` `software_trap_number` `software_trap_number` `software_trap_number`		Synonym: `tcc`
	`tvc` `tvs` `ta`	`software_trap_number` `software_trap_number` `software_trap_number`		Synonym: `t`
`TADDcc` `TSUBcc`	`taddcc` `tsubcc`	reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd	Tagged add and modify `icc`
`TADDccTV` `TSUBccTV`	`taddcctv` `tsubcctv`	reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd	Tagged add and modify `icc` and trap on overflow
`UDIV`	`udiv`	reg_rs1, reg_or_imm, reg_rd	Unsigned divide
`UDIVcc`	`udivcc`	reg_rs1, reg_or_imm, reg_rd	Unsigned divide and modify `icc`
`UMUL`	`umul`	reg_rs1, reg_or_imm, reg_rd	Unsigned multiply
`UMULcc`	`umulcc`	reg_rs1, reg_or_imm, reg_rd	Unsigned multiply and modify `icc`
`UNIMP`	`unimp`	`const22`	Illegal instruction
`WRASR`	`wr`	reg_or_imm, `%asr`n_rs1
`WRY`	`wr`	reg_rs1, reg_or_imm, `%y`		See synthetic instructions
`WRPSR`	`wr`	reg_rs1, reg_or_imm, `%psr`		See synthetic instructions
`WRWIM`	`wr`	reg_rs1, reg_or_imm, `%wim`		See synthetic instructions
`WRTBR`	`wr`	reg_rs1, reg_or_imm, `%tbr`		See synthetic instructions
`XNOR` `XNORcc`	`xnor` `xnorcc`	reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd	Exclusive `nor`
`XOR` `XORcc`	`xor` `xorcc`	reg_rs1, reg_or_imm, reg_rd reg_rs1, reg_or_imm, reg_rd	Exclusive `or`

5.3 Floating-Point Instruction

Table 5–4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.

Table 5–4


SPARC	Mnemonic [Types of Operands are denoted by the following lower-case letters:`i` integer`s` single`d` double`q` quad]	Argument List	Description
`FiTOs`	`fitos`	freg_rs2, freg_rd	Convert integer to single
`FiTOd`	`fitod`	freg_rs2, freg_rd	Convert integer to double
`FiTOq`	`fitoq`	freg_rs2, freg_rd	Convert integer to quad
`FsTOi`	`fstoi`	freg_rs2, freg_rd	Convert single to integer
`FdTOi`	`fdtoi`	freg_rs2, freg_rd	Convert double to integer
`FqTOi`	`fqtoi`	freg_rs2, freg_rd	Convert quad to integer
`FsTOd`	`fstod`	freg_rs2, freg_rd	Convert single to double
`FsTOq`	`fstoq`	freg_rs2, freg_rd	Convert single to quad
`FdTOs`	`fdtos`	freg_rs2, freg_rd	Convert double to single
`FdTOq`	`fdtoq`	freg_rs2, freg_rd	Convert double to quad
`FqTOd`	`fqtod`	freg_rs2, freg_rd	Convert quad to double
`FqTOs`	`fqtos`	freg_rs2, freg_rd	Convert quad to single
`FMOVs`	`fmovs`	freg_rs2, freg_rd	Move
`FNEGs`	`fnegs`	freg_rs2, freg_rd	Negate
`FABSs`	`fabss`	freg_rs2, freg_rd	Absolute value
`FSQRTs` `FSQRTd` `FSQRTq`	`fsqrts` `fsqrtd` `fsqrtq`	freg_rs2, freg_rd freg_rs2, freg_rd freg_rs2, freg_rd	Square root
`FADDs` `FADDd` `FADDq`	`fadds` `faddd` `faddq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Add
`FSUBs` `FSUBd` `FSUBq`	`fsubs` `fsubd` `fsubq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Subtract
`FMULs` `FMULd` `FMULq`	`fmuls` `fmuld` `fmulq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Multiply
`FdMULq`	`fmulq`	freg_rs1, freg_rs2, freg_rd	Multiply double to quad
`FsMULd`	`fsmuld`	freg_rs1, freg_rs2, freg_rd	Multiply single to double
`FDIVs` `FDIVd` `FDIVq`	`fdivs` `fdivd` `fdivq`	freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd freg_rs1, freg_rs2, freg_rd	Divide
`FCMPs` `FCMPd` `FCMPq`	`fcmps` `fcmpd` `fcmpq`	freg_rs1, freg_rs2 freg_rs1, freg_rs2 freg_rs1, freg_rs2	Compare
`FCMPEs` `FCMPEd` `FCMPEq`	`fcmpes` `fcmped` `fcmpeq`	freg_rs1, freg_rs2 freg_rs1, freg_rs2 freg_rs1, freg_rs2	Compare, generate exception if not ordered

5.4 Coprocessor Instructions

All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. The data types supported by the coprocessor are coprocessor-dependent. Operand alignment is also coprocessor-dependent. Coprocessor-operate instructions are described in Table 5–5.

If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0, or if a coprocessor is not present, a cpopn instruction causes a cp_disabled trap.

The conditions that cause a cp_exception trap are coprocessor-dependent.

Table 5–5


SPARC	Mnemonic	Argument List	Name	Comments
`CPop1`	`cpop1`	opc, reg_rs1, reg_rs2, reg_rd	Coprocessor operation
`CPop2`	`cpop2`	opc, reg_rs1, reg_rs2, reg_rd	Coprocessor operation	May modify `ccc`

5.5 Synthetic Instructions

Table 5–6 describes the mapping of synthetic instructions to hardware instructions.

Table 5–6


Synthetic Instruction		Hardware Equivalent(s)		Comment
`btst`	reg_or_imm, reg_rs1	`andcc`	reg_rs1, reg_or_imm, `%g0`	Bit test
`bset`	reg_or_imm, reg_rd	`or`	reg_rd, reg_or_imm, reg_rd	Bit set
`bclr`	reg_or_imm, reg_rd	`andn`	reg_rd, reg_or_imm, reg_rd	Bit clear
`btog`	reg_or_imm, reg_rd	`xor`	reg_rd, reg_or_imm, reg_rd	Bit toggle
`call`	reg_or_imm	`jmpl`	reg_or_imm, `%o7`
`clr`	reg_rd	`or`	`%g0`, `%g0`, reg_rd	Clear (zero) register
`clrb`	[address]	`stb`	`%g0`, [address]	Clear byte
`clrh`	[address]	`st`	`%g0`, [address]	Clear halfword
`clr`	[address]	`st`	`%g0`, [address]	Clear word
`cmp`	reg, reg_or_imm	`subcc`	reg_rs1, reg_or_imm, `%g0`	Compare
`dec`	reg_rd	`sub`	reg_rd, 1, reg_rd	Decrement by 1
`dec`	const13, reg_rd	`sub`	reg_rd, const13, reg_rd	Decrement by const13
`deccc`	reg_rd	`subcc`	reg_rd, 1, reg_rd	Decrement by 1 and set `icc`
`deccc`	const13, reg_rd	`subcc`	reg_rd, const13, reg_rd	Decrement by const13 and set `icc`
`inc`	reg_rd	`add`	reg_rd, 1, reg_rd	Increment by 1
`inc`	const13, reg_rd	`add`	reg_rd, const13, reg_rd	Increment by const13
`inccc`	reg_rd	`addcc`	reg_rd, 1, reg_rd	Increment by 1 and set `icc`
`inccc`	const13, reg_rd	`addcc`	reg_rd, const13, reg_rd	Increment by const13 and set `icc`
`jmp`	address	`jmpl`	address, `%g0`
`mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov` `mov`	reg_or_imm,reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 reg_or_imm, `%y` reg_or_imm, `%psr` reg_or_imm, `%wim` reg_or_imm, `%tbr`	`or` `rd` `rd` `rd` `rd` `wr` `wr` `wr` `wr`	`%g0`, reg_or_imm, reg_rd `%y`, reg_rs1 `%psr`, reg_rs1 `%wim`, reg_rs1 `%tbr`, reg_rs1 `%g0`,reg_or_imm,`%y` `%g0`,reg_or_imm,`%psr` `%g0`,reg_or_imm,`%wim` `%g0`,reg_or_imm,`%tbr`
`not`	reg_rs1, reg_rd	`xnor`	reg_rs1, `%g0`, reg_rd	One's complement
`not`	reg_rd	`xnor`	reg_rd, `%g0`, reg_rd	One's complement
`neg`	reg_rs1, reg_rd	`sub`	`%g0`, reg_rs2, reg_rd	Two's complement
`neg`	reg_rd	`sub`	`%g0`, reg_rd, reg_rd	Two's complement
`restore`		`restore`	`%g0`, `%g0`, `%g0`	Trivial restore
`save`		`save`	`%g0`, `%g0`, `%g0`	Trivial save trivial save should only be used in supervisor code!
`set`	value,reg_rd	`or`	`%g0`, value, reg_rd	if -4096 ≤value ≤ 4095 Do not use the `set` synthetic instruction in an instruction delay slot.
`set`	value,reg_rd	`sethi`	`%hi`(value), reg_rd	if ((value & 0x3ff) == 0)
`set`	value, reg_rd	`sethi` `or`	`%hi`(value), reg_rd; reg_rd, `%lo`(value), reg_rd	otherwise Do not use the `set` synthetic instruction in an instruction delay slot.
`skipz`		`bnz,a .+8`		if z is set, ignores next instruction
`skipnz`		`bz,a .+8`		if z is not set, ignores next instruction
`tst`	reg	`orcc`	reg_rs1, `%g0`, `%g0`	test

5.6 V8/V9 Natural Pseudo Instructions

Table 5–7 describes the V8/V9 natural pseudo instructions that will help increase the portability of your assembly code from V8/V8plus to V9.

Table 5–7


Pseudo Instructions	-xarch=
Pseudo Instructions	V8/V8plus [Indicates default setting]	V9
`ldn`	ld	ldx
`stn`	`st`	stx
`ldna`	lda	ldxa
`stna`	`sta`	stxa
`setn`	set	`setx`
setnhi	sethi	setxhi
casn	cas	casx
slln	sll	sllx
srln	srl	srlx
sran	sra	srax
clrn	clr	clrx

Note –

Depending on the value set for the -xarch option, the assembler substitutes the appropriate pseudo instruction.