CHAPTER 7

Color Graphics Frame Buffer Test (cg14test)

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cg14test checks the cg14 frame buffer card. The cg14test is specific to the VSIMM (Video SIMM) devices in the SPARCstation 10 SX and the SPARCstation 20 SX.

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Caution - Due to possible conflicts between SunVTS cg14 frame buffer tests and OPEN LOOK applications that use the cg14 frame buffer, the following restrictions apply when running cg14test:

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To start SunVTS with vtsui, but without vtsk, you must add the host name to xhost as:

xhost + <hostname>.

• Do not run graphic applications other than OPEN LOOK while SunVTS is running frame buffer tests.
• Do not run OPEN LOOK programs that generate video updates outside or on top of the SunVTS window.
• Do not close the SunVTS window to an icon while it is running frame buffer tests.

  Ensure that the frame buffer locking option is enabled from the Options window (see the section about testing frame buffers in SunVTS 2.1 User's Guide for details).

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cg14test Groups

There are nine test groups with cg14test:

• MDI and VBC Chip Control Registers
• Memory Chips
• MDI Chip Cursor Registers
• MDI Chip CLUT Registers
• DAC Chip Registers
• MDI Chip XLU Registers
• CG14 Display (visual only)
• MDI Chip Testmode Readback in 8-bit mode
• Driver IOCTLs

TABLE 7-1 cg14

cg14 Groups	Description
Hardware (Groups 1-6)	Testing is done by opening /dev/fbs/cgfourteenX, mmapping (R/W shared) the MDI Control Address Space, modifying the target test location (using direct writes to the mmap'ed address space), reading from the mmapped address space for verification, and closing the device.
Visual Pattern (Group 7)	Testing is done by loading a visual pattern of 256 colors, then rotating the pattern around by adjusting CLUT1. This subtest must be verified visually.
Data Propagation (Group 8)	Testing is done by loading the frame buffer (FB) memory with four neutral data patterns, then setting a target FB pixel with data that triggers the test mode readback latch. The result is read from the readback register after vertical blanking occurs. Two different trigger patterns are used at each FB pixel. All four MDI pixel paths (A - D) are used, and the pixel locations for each trigger are designed to detect gross MDI input data opens or short, VRAM SAM addressing, and VRAM-to-SAM transfer addressing. The screen shows four horizontal bars, which are either greyscale or colored. These bars change each time the trigger data is inverted, and as it completes the testing of a raster pattern. NOTE -- If the resolution and VRAM size permits, 8-bits per pixel mode are tested.

TABLE 7-1 cg14(Continued)

cg14 Groups	Description
Driver (Group 9)	Test all IOCTL calls that have not yet been used to verify proper driver communication to the hardware. Call the driver to perform a hardware update, and then confirm that the update was successful by using the complementary driver read, or reading the mmap'ed address space and comparing it against the stimulus. cg14test performs the appropriate steps before and after each test (if possible) to maintain context and prevent visual confusion by saving the register data before it is overwritten, disabling video (if possible), performing the specific test, and restoring the saved register data information. The data used for register testing is optimized to include all 0's, all 1's, and walking a 1 through each bit being tested.
MDI and VBC Chip Control Registers (Group 1)	Master Control Register bits 7-0 write/read verify Packed Pixel Register bits 3-0 write/read verify Master Status Register bits 7-4 read-only verify 0x00 and 0x30 occur Horizontal Blank Start Register bits 9-0 write/read verify Horizontal Blank Clear Register bits 9-0 write/read verify Horizontal Sync Set Register bits 9-0 write/read verify Horizontal Sync Clear Register bits 9-0 write/read verify Composite Sync Clear Register bits 9-0 write/read verify Vertical Blank Start Register bits 11-0 write/read verify Vertical Blank Clear Register bits 11-0 write/read verify Vertical Sync Set Register bits 11-0 write/read verify Vertical Sync Clear Register bits 11-0 write/read verify Transfer Cycle Set Register bits 9-0 write/read verify (MDI revision 0 only) Transfer Cycle Clear Register bits 9-0 write/read verify (MDI revision 0 only) Fault Status Address Register bits 15-0 write/read verify Auto-increment Address Space Register bits 7-0 write/read verify Video Base Register bits 23-12 write/read verify
Memory Chips (Group 2)	The Memory Chips test group includes VRAM Testing, Memory Retention, and Test Write Recovery. VRAM Testing The Data Bus Test uses 18 NTA patterns (Nair, Thatte, and Abraham's testing procedure for RAM) to check for data and address faults. This test is performed in MDI_CHUNKY_XBGR_MAP access mode only. See Table 7-2.

TABLE 7-1 cg14(Continued)

cg14 Groups	Description
Memory Chips (Group 2) Continued	VRAM Testing (Continued The test ascends through the FB memory, clearing it to 0's. The NTA pattern test number x reads a location to make sure test data y is present. It then writes new data z to that location. The location ascends through the FB sequentially. See Table 7-2. Memory Retention VRAM Data Retention checks for gross problems with the VRAM refresh. Since refresh is active during this test, no retention problems should occur unless the refresh is defective. This test turns off the video, writes 0's to all the VRAM, waits the specified memory_hold time (the default is five seconds), then reads and compares all VRAM data. This process is repeated with data of f's, then the video is restored and the test is complete. There are two new command line parameters related to this test: R=number and H=number. R= lets the user specify the refresh interval from 128-1023. The time between refresh cycles and the system default is 123. H= lets the user specify the retention test hold time in seconds. Test Write Recovery A write recovery test is used in all the EMC mapping modes to write data to 0's followed by immediately reading that data location to see if the VRAM can recover from a write correctly. This is done to all sequential ascending locations. Next, a second independent pass of memory is made with the complementary data of 0xffffffff being written to descending locations of the FB memory buffer. The EMC mapping access modes are: MDI_CHUNKY_XGBR_MAP MDI_CHUNKY_BGR_MAP MDI_PLANAR_X16_MAP MDI_PLANAR_C16_MAP MDI_PLANAR_X32_MAP MDI_PLANAR_B32_MAP MDI_PLANAR_G32_MAP MDI_PLANAR_R32_MAP

TABLE 7-1 cg14(Continued)

cg14 Groups	Description
MDI Chip Cursor Registers (Group 3)	The MDI Chip Cursor Registers are: Cursor Plane 0 Register bits 31-0 write/read verify Cursor Plane 1 Register bits 31-0 write/read verify Cursor Plane 0 Register bits 31-0 write/read verify (with auto increment) Cursor Plane 1 Register bits 31-0 write/read verify (with auto increment Cursor Control Register bits 2-0 write/read verify Cursor Color Register 1 bits 28-0 write/read verify Cursor Color Register 2 bits 28-0 write/read verify X-Cursor Location Register bits 11-0 write/read verify Y-Cursor Location Register bits 11-0 write/read verify Cursor Plane 0 Non-Auto Registers test Cursor Plane 0 Auto Registers test Cursor Plane 1 Non-Auto Registers test Cursor Plane 1 Auto Registers test Cursor Planes Retry A test Cursor Planes Retry B test
MDI Chip CLUT Registers (Group 4)	The MDI Chip CLUT Registers are: LUT1 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT1 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT1D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT1D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT2 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT2 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT2D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT2D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT3 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT3 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT3D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT3D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment)

TABLE 7-1 cg14(Continued)

cg14 Groups	Description
DAC Chip Registers (Group 5)	The DAC Chip Registers test group includes the RAMDAC registers and control registers. RAMDAC Registers Address Register bits 7-0 (0x7 maximum) write/read verify Mode Register bits 7-0 (skip bit 5) bits write/read verify Control Registers ID Register bits 7-0 r/o verify data is 0x8C Pixel-Mask Register bits 7-0 write/read verify (skipped if dac rev = 2) Command2 Register bits 7-0 write/read verify (skipped if dac rev = 2) Command3 Register bits 7-0 write/read verify (skipped if dac rev = 2)
MDI Chip XLUT Registers (Group 6)	The MDI Chip XLUT Registers are: XLUT Registers 0-255 bits 7-0 write/read verify XLUT Registers 0-255 bits 7-0 write/read verify (with auto increment) XLUTD Registers 0-255 bits 7-0 write/read verify XLUTD Registers 0-255 bits 7-0 write/read verify (with auto increment)
CG14 Display (visual only) Group 7)	This visually displays 256 boxes on the screen (each in a different color), and then shifts the CLUT1 entries giving the visual impression of the pattern mirroring itself from left to right horizontally. The pattern then rotates up, down, followed by mirroring itself horizontally left to right.
MDI Chip Test Mode Readback Register (Group 8)	Test Mode Readback Register bits 23-0 read-only verify

TABLE 7-1 cg14(Continued)

cg14 Groups	Description
Driver IOCTLs (Group 9)	MDI_GET_CFGINFO check # of CLUT's, pixel height, pixel width, and pixel mode against hardware FBIOGATTR check real_type, fb_height, fb_width, fb_depth, fb_cmsize, and fb_size against cfginfo values FBIOGTYPE check fb_type, fb_height, fb_width, fb_depth,fb_size, and fb_cmsize against driver defines or cfginfo values FBIOGVIDEO check status returned against hardware FBIOSVIDEO set off, off, on, on, off verifying against hardware FBIOVERTICAL (imbedded in FBIOSVIDEO) MDI_VRT_CNTL turn off, off, on, on, off the video interrupt enable and verify the hardware agreesMDI_SET_PIXELMODE set different modes and verify against the hardware MDI_SET_PPR set the different modes and verify against the hardware MDI_SET_COUNTERS set HSS, HSC, XCC, HBC, XCS, HBS, CSC, VSS, VSC, VBC, VBS, HCT, and VCT then verify against hardware MDI_SET_XLUT set xlut and verify against hardware MDI_GET_XLUT get xlut and verify against hardware MDI_SET_CLUT set clut (1-3 as applicable) and verify against hardware MDI_GET_CLUT get clut (1-3 as applicable) and verify against hardware FBIOPUTCMAP set and verify clut1 matches FBIOGETCMAP verify clut1 matches get FBIOSATTR set emu_type to FBTYPE_MDICOLOR and verify FBIOGATTR check FBIOGCURMAX verify x and y size match driver defines FBIOSCURSOR verify set at 3 locations matches hardware FBIOGCURSOR verify driver knows what set(s) just did FBIOSCURPOS verify set at three locations matches hardware FBIOGCURPOS verify driver knows what set(s) just did MDI_SET_CURSOR set then check CCR, XCU, and YCU cursor hardware registers

TABLE 7-2 cg14test

NTA Test Pattern Number = x	Test Data = y	New Data = z
1.0	0x00000000	0x01010101
1.5	0x01010101	0xffffffff
2.1	0xffffffff	0xf1f1f1f1
2.2	0xf1f1f1f1	0x33333333
3.1	0x33333333	0xf0f0f0f0

TABLE 7-2 cg14test(Continued)

NTA Test Pattern Number = x	Test Data = y	New Data = z
3.2	0xf0f0f0f0	0x0f0f0f0f
4.1	0x0f0f0f0f	0x55555555
4.2	0x55555555	0xaaaaaaaa
5.1	0xaaaaaaaa	0x05050505 (1x) 0x88888888 (2x)
5.2	0x88888888	0xf5f5f5f5
6.1	0xf5f5f5f5	0x00000000 (1x) 0x5f5f5f5f (2x)
6.2	0x5f5f5f5f	0x11111111
7.1	0x11111111	0x00000000 (1x) 0xcccccccc (2x)
7.2	0xcccccccc	0xdbdbdbdb
8.1	0xdbdbdbdb	0x6d6d6d6d
8.2	0x6d6d6d6d	0x6b6b6b6b
9.1	0x6b6b6b6b	0x0000000
9.2	0x00000000	-

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cg14test Options

TABLE 7-3 cg14

cg14 Groups	Description
Hardware (Groups 1-6)	Testing is done by opening /dev/fbs/cgfourteenX, mmapping (R/W shared) the MDI Control Address Space, modifying the target test location (using direct writes to the mmap'ed address space), reading from the mmapped address space for verification, and closing the device.
Visual Pattern (Group 7)	Testing is done by loading a visual pattern of 256 colors, then rotating the pattern around by adjusting CLUT1. This subtest must be verified visually.

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
Data Propagation (Group 8)	Testing is done by loading the frame buffer (FB) memory with four neutral data patterns, then setting a target FB pixel with data that triggers the test mode readback latch. The result is read from the readback register after vertical blanking occurs. Two different trigger patterns are used at each FB pixel. All four MDI pixel paths (A - D) are used, and the pixel locations for each trigger are designed to detect gross MDI input data opens or short, VRAM SAM addressing, and VRAM-to-SAM transfer addressing. The screen shows four horizontal bars, which are either greyscale or colored. These bars change each time the trigger data is inverted, and as it completes the testing of a raster pattern. NOTE -- If the resolution and VRAM size permits, 8-bits per pixel mode are tested.
Driver (Group 9)	Test all IOCTL calls that have not yet been used to verify proper driver communication to the hardware. Call the driver to perform a hardware update, and then confirm that the update was successful by using the complementary driver read, or reading the mmap'ed address space and comparing it against the stimulus. cg14test performs the appropriate steps before and after each test (if possible) to maintain context and prevent visual confusion by saving the register data before it is overwritten, disabling video (if possible), performing the specific test, and restoring the saved register data information. The data used for register testing is optimized to include all 0's, all 1's, and walking a 1 through each bit being tested.

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
MDI and VBC Chip Control Registers (Group 1)	Master Control Register bits 7-0 write/read verify Packed Pixel Register bits 3-0 write/read verify Master Status Register bits 7-4 read-only verify 0x00 and 0x30 occur Horizontal Blank Start Register bits 9-0 write/read verify Horizontal Blank Clear Register bits 9-0 write/read verify Horizontal Sync Set Register bits 9-0 write/read verify Horizontal Sync Clear Register bits 9-0 write/read verify Composite Sync Clear Register bits 9-0 write/read verify Vertical Blank Start Register bits 11-0 write/read verify Vertical Blank Clear Register bits 11-0 write/read verify Vertical Sync Set Register bits 11-0 write/read verify Vertical Sync Clear Register bits 11-0 write/read verify Transfer Cycle Set Register bits 9-0 write/read verify (MDI revision 0 only) Transfer Cycle Clear Register bits 9-0 write/read verify (MDI revision 0 only) Fault Status Address Register bits 15-0 write/read verify Auto-increment Address Space Register bits 7-0 write/read verify Video Base Register bits 23-12 write/read verify
Memory Chips (Group 2)	The Memory Chips test group includes VRAM Testing, Memory Retention, and Test Write Recovery. VRAM Testing The Data Bus Test uses 18 NTA patterns (Nair, Thatte, and Abraham's testing procedure for RAM) to check for data and address faults. This test is performed in MDI_CHUNKY_XBGR_MAP access mode only. See Table 7-2.

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
Memory Chips (Group 2) Continued	VRAM Testing (Continued The test ascends through the FB memory, clearing it to 0's. The NTA pattern test number x reads a location to make sure test data y is present. It then writes new data z to that location. The location ascends through the FB sequentially. See Table 7-2. Memory Retention VRAM Data Retention checks for gross problems with the VRAM refresh. Since refresh is active during this test, no retention problems should occur unless the refresh is defective. This test turns off the video, writes 0's to all the VRAM, waits the specified memory_hold time (the default is five seconds), then reads and compares all VRAM data. This process is repeated with data of f's, then the video is restored and the test is complete. There are two new command line parameters related to this test: R=number and H=number. R= lets the user specify the refresh interval from 128-1023. The time between refresh cycles and the system default is 123. H= lets the user specify the retention test hold time in seconds. Test Write Recovery A write recovery test is used in all the EMC mapping modes to write data to 0's followed by immediately reading that data location to see if the VRAM can recover from a write correctly. This is done to all sequential ascending locations. Next, a second independent pass of memory is made with the complementary data of 0xffffffff being written to descending locations of the FB memory buffer. The EMC mapping access modes are: MDI_CHUNKY_XGBR_MAP MDI_CHUNKY_BGR_MAP MDI_PLANAR_X16_MAP MDI_PLANAR_C16_MAP MDI_PLANAR_X32_MAP MDI_PLANAR_B32_MAP MDI_PLANAR_G32_MAP MDI_PLANAR_R32_MAP

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
MDI Chip Cursor Registers (Group 3)	The MDI Chip Cursor Registers are: Cursor Plane 0 Register bits 31-0 write/read verify Cursor Plane 1 Register bits 31-0 write/read verify Cursor Plane 0 Register bits 31-0 write/read verify (with auto increment) Cursor Plane 1 Register bits 31-0 write/read verify (with auto increment Cursor Control Register bits 2-0 write/read verify Cursor Color Register 1 bits 28-0 write/read verify Cursor Color Register 2 bits 28-0 write/read verify X-Cursor Location Register bits 11-0 write/read verify Y-Cursor Location Register bits 11-0 write/read verify Cursor Plane 0 Non-Auto Registers test Cursor Plane 0 Auto Registers test Cursor Plane 1 Non-Auto Registers test Cursor Plane 1 Auto Registers test Cursor Planes Retry A test Cursor Planes Retry B test
MDI Chip CLUT Registers (Group 4)	The MDI Chip CLUT Registers are: LUT1 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT1 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT1D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT1D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT2 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT2 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT2D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT2D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT3 Registers 0-255 bits 31-27 & 23-0 write/read verify LUT3 Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment) LUT3D Registers 0-255 bits 31-27 & 23-0 write/read verify LUT3D Registers 0-255 bits 31-27 & 23-0 write/read verify (with auto increment)

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
DAC Chip Registers (Group 5)	The DAC Chip Registers test group includes the RAMDAC registers and control registers. RAMDAC Registers Address Register bits 7-0 (0x7 maximum) write/read verify Mode Register bits 7-0 (skip bit 5) bits write/read verify Control Registers ID Register bits 7-0 r/o verify data is 0x8C Pixel-Mask Register bits 7-0 write/read verify (skipped if dac rev = 2) Command2 Register bits 7-0 write/read verify (skipped if dac rev = 2) Command3 Register bits 7-0 write/read verify (skipped if dac rev = 2)
MDI Chip XLUT Registers (Group 6)	The MDI Chip XLUT Registers are: XLUT Registers 0-255 bits 7-0 write/read verify XLUT Registers 0-255 bits 7-0 write/read verify (with auto increment) XLUTD Registers 0-255 bits 7-0 write/read verify XLUTD Registers 0-255 bits 7-0 write/read verify (with auto increment)
CG14 Display (visual only) Group 7)	This visually displays 256 boxes on the screen (each in a different color), and then shifts the CLUT1 entries giving the visual impression of the pattern mirroring itself from left to right horizontally. The pattern then rotates up, down, followed by mirroring itself horizontally left to right.
MDI Chip Test Mode Readback Register (Group 8)	Test Mode Readback Register bits 23-0 read-only verify

TABLE 7-3 cg14(Continued)

cg14 Groups	Description
Driver IOCTLs (Group 9)	MDI_GET_CFGINFO check # of CLUT's, pixel height, pixel width, and pixel mode against hardware FBIOGATTR check real_type, fb_height, fb_width, fb_depth, fb_cmsize, and fb_size against cfginfo values FBIOGTYPE check fb_type, fb_height, fb_width, fb_depth,fb_size, and fb_cmsize against driver defines or cfginfo values FBIOGVIDEO check status returned against hardware FBIOSVIDEO set off, off, on, on, off verifying against hardware FBIOVERTICAL (imbedded in FBIOSVIDEO) MDI_VRT_CNTL turn off, off, on, on, off the video interrupt enable and verify the hardware agreesMDI_SET_PIXELMODE set different modes and verify against the hardware MDI_SET_PPR set the different modes and verify against the hardware MDI_SET_COUNTERS set HSS, HSC, XCC, HBC, XCS, HBS, CSC, VSS, VSC, VBC, VBS, HCT, and VCT then verify against hardware MDI_SET_XLUT set xlut and verify against hardware MDI_GET_XLUT get xlut and verify against hardware MDI_SET_CLUT set clut (1-3 as applicable) and verify against hardware MDI_GET_CLUT get clut (1-3 as applicable) and verify against hardware FBIOPUTCMAP set and verify clut1 matches FBIOGETCMAP verify clut1 matches get FBIOSATTR set emu_type to FBTYPE_MDICOLOR and verify FBIOGATTR check FBIOGCURMAX verify x and y size match driver defines FBIOSCURSOR verify set at 3 locations matches hardware FBIOGCURSOR verify driver knows what set(s) just did FBIOSCURPOS verify set at three locations matches hardware FBIOGCURPOS verify driver knows what set(s) just did MDI_SET_CURSOR set then check CCR, XCU, and YCU cursor hardware registers

FIGURE 7-1 cg14test

TABLE 7-4 cg14test

cg14test Options	Description
FB Locking	See the section about Testing Multiple Frame Buffers in the SunVTS 2.1 User's Guide for details
Long Test	When enabled, the color bar screen(s) in the MDI Testmode Readback test checks all SAM transfers in clock=0 mode and clock=1 mode. If Long test is disabled, clock=1 runs checks on the first eight addresses and first SAM transfer only
Processor Affinity	For multiprocessor systems, indicates the processor to be tested

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cg14test Command Line Syntax

/opt/SUNWvts/bin/cg14test standard_arguments -o dev=device_name,
lock=E(nable)/D(isable),L,I

TABLE 7-5 cg14test

Argument	Explanation
dev=device_name	Specifies the path of the cg14 device file to be tested; for example: /dev/fbs/device_name
lock=E(nable)/ D(isable)	Enables and disables the window system locking option. See the Testing Multiple Frame Buffers sections in the SunVTS 2.1 User's Guide for details. Do not use when device is the window system display.
L	Enables the long TMRB test.
I	Enables optional driver ioctl tests for cursor. Note- Do not move the mouse during the cg14test when you run this option.

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cg14test Test Modes

Due to the nature of graphic tests, reading from or writing to the frame buffer during graphic tests will disturb user operation. This test is only available in Functional test.

The Functional test uses all subtests to test the cg14 frame buffer. The user can select the long mode for TRMB subtest.

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cg14test Error Messages

TABLE 7-6 cg14test

	Error Message	Probable Cause(s)	Suggested Action (if applicable)
6002	MDI <name> register = <number>	CG14 video board
6004	MDI Cursor planes retry test maximum retry limit exceeded	CG14 video board
6006	<name> error message	CG14 video board
6008	Failed open of file <name>,	Disk
	errno=<number>	CPU board
6010	Failed write to file	CG14 video board
	<name>, errno=<number>	CPU board
		Disk
6012	Failed close of file	Disk
	<name>, errno=<number>	CPU board
6014	MDI chip TestMode Readback, <number>-bit <name> mode, offset= <number> pixelpipe=<name> clock=<number> exp=<number> obs=<number>
6016	MEM (<name>), Data	CG14 video board
	Retention offset= <number> exp=<number> obs=<number>	CPU board
6018	MEM (<name>), NTA <name>	CG14 video board
	offset= <number> exp=<number> obs=<number>	CPU board
6020	MEM (<name>), WRRD <name>	CG14 video board
	offset= <number> exp=<number> obs=<number>	CPU board

TABLE 7-6 cg14test(Continued)

	Error Message	Probable Cause(s)	Suggested Action (if applicable)
6022	failed, mapping <name>	CG14 device file
	space, errno = <number>	SunOS
		CG14 video board
		CPU board
6024	MEM (<name>), WRRD <name>	SunOS
	offset= <number> exp=<number> obs=<number>	CG14 video board
		CPU board
6026	VBC Control Register	CG14 video board
	exp=<number> obs=<number>	CPU board
8002	<name> is an invalid parameter for <name>!	Operator error
8004	unable to close device	CG14 device file
	<name>	SunOS
		CG14 video board
8006	invalid CG14 device type	CG14 device file
	from <name>	SunOS
		CG14 video board
8008	IOCTL Error: <name>	CPU board
		CG14 video board
8008	IOCTL(<name>) <name>	CPU board
		CG14 video board
8010	unable to unlock OL windows	SunOS
		Operator error
8012	IOCTL(<name>,CLUT<number>)	CG14 device file
	<name>	SunOS
		CG14 video board
8014	unable to open CG14 device	Incorrect device name
	<name>	No existing device
		CG14 video board