.........................Index


A
address
...phase	7
...strobe	5
arbitration	5, 7, 8
arbitration fairness algorithm (PCI)	8
arbitration phase (SBus)	6
B
basic transaction cycle	6, 7
burst transfer
...protocol	7
burst transfers	7
bus time-outs	5
bus transaction participants	1
C
controller (SBus)	5
D
data
...acknowledgment rate	6
...phase	7
data transfer
...count	5
...rate	6
default transfer	5
dynamic bus-sizing	7
E
extended transfer	5
...information phase	7
...mode	7
I
initiator	5, 7
L
latency	8
M
master (bus)	5
master (PCI)	5
master-initiated transaction types	5
P
PCI arbiter	5
power consumption	1, 2, 3
power dissipation	1, 2


protocol	6
S
SBus master	5
SBus system clock	5
SIZ[2:0]	7
slave	6
...cycle	7
...selects	5
T
target	6
target (PCI)	6
transaction termination (PCI)	5
transfer phase	7
transfers, 64-bit	7
translation	5
translation phase	6
V
virtual address translation	5