PCI FCode PROM Header Format

The PCI FCode PROM header format is described in Table 1-1.

Table 1-1

Header	Format
PCI expansion PROM header	28 bytes
PCI data structure	24 bytes
FCode	(8 Byte FCode header + FCode code bytes)

If you are dloading or booting your FCode image on a Solaris 2.5.1 or 2.6 system, you must replace the a.out header by an ELF header.

The fakeboot utility can add an ELF header based on parameters that you pass to fakeboot. The addhdr utility can also add either an a.out or ELF header, in addition to adding a PCI header and PCI data structure.

The PCI Expansion PROM Header Format

The PCI expansion PROM header format (28 bytes) is as follows:

Table 1-2

Byte Offset	Value	Description
00	55(h)	PROM signature byte one.
01	aa(h)	PROM signature byte two.
02-03	34 00 (h)	SPARC reserved value
04-17	00 00	Reserved for processor architecture-unique data.
18-19	1c 00	Pointer to PCI data structure (assuming PCI data structure follows immediately after PCI expansion PROM Header).
1A-1B	00 00	Pad bytes.

PCI Expansion PROM Data Structure Format

The PCI expansion PROM data structure (24 bytes) is described in Table 1-2.

Table 1-3

Byte offset	Description /(Hex. value)
00-03	signature: P C I R (50 43 49 52)
04-05	vendor id
06-07	device id
08-09	Pointer to Vital Product Data
0A-0B	PCI data structure length (18 00)
0C	PCI data structure revision.
0D	Programming interface code
0E	Subclass code
0F	Class code
10-11	Image length in 512 bytes
12-13	Revision level of code/data

Table 1-3 (Continued)

Byte offset	Description /(Hex. value)
14	Code type (01)
15	Indicator byte. For last image (80)
16-17	Reserved (00 00)

Table 1-3 shows a dump of initial bytes in a PCI FCode PROM with an a.out header in the first 32 bytes.

Table 1-4

Hex Addr	Hex Value
00000	01 03 01 07 00 00 46 98 00 00 00 00 00 00 00 00
00010	00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00
00020	55 aa 34 00 00 00 00 00 00 00 00 00 00 00 00 00
00030	00 00 00 00 00 00 00 00 1c 00 00 00 50 43 49 52
00040	8e 10 01 10 00 c0 18 00 00 00 00 02 7e 00 00 01
00050	01 80 00 00 fd 03 18 6e 00 00 46 64 xx xx xx xx

For the PROM above, the vendor id is 0x108e, the device id is 0x1001, the pointer to Vital Product Data is 0xc000, class code is 0x02,subclass code is 0, programming interface code is 0, image length (in 512 bytes) is 0x7e, FCode length is 0x4664 bytes, xx..... are FCode data.

Format of Physical Address in "reg" Property

• For PCI, the "reg" property value has 5 32-bit numbers:
• - phys.hi
• , phys.mid,
• phys.lo,
• size.hi
• , size.lo.
• The size.hi and size.lo are values for a register size the address and type of which are defined by phys.hi, phys.mid, and phys.low.

The format of the physical address in the "reg" property is as follows:

phys.hi cell:	npt000ss bbbbbbbb dddddfff rrrrrrrr
phys.mid cell:	hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
phys.low cell:	LLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL

where

• n is 0 if the address is relocatable; 1 otherwise.
• p is 1 if the addressable region is prefetchable; 0 otherwise.
• t is 1 if the address is aliased (for non-relocatable I/O), below 1MByte (for memory), or below 64KBytes (for relocatable I/O).
• ss=00 ==> configuration space.
• ss=01 ==> I/O space.
• ss=10 ==> 32 bit memory space.
• ss=11 ==> 64 bit memory space.
• bbbbbbbb is an 8-bit bus number (assigned by the CPU PROM at probe time).
• ddddd is a 5-bit device number.
• fff is a 3-bit function number.
• rrrrrrrr is an 8-bit register number.
• hh..hh is a 32-bit unsigned number, most significant bits.
• LL..LL is a 32-bit unsigned number, least significant bits.

PCI Device Configuration Register Access

To find the address to use for configuration register access on your PCI device, look in the format for the physical address of the "reg" property. You can use the phys.hi cell of the first entry in the "reg" property, as the base address for the configuration space.

The first entry in the "reg" property must be the configuration space entry (bbbb.bbbb.dddd.dfff.0000.0000 binary). Use that (or any other method), to obtain the values of bbbb.bbbb, ddddd and fff for your device. Then use:

ok "<parent-pci-bus-node>" select-dev
ok <bbbb.bbbb.dddd.dfff>XX config-l@

(XX is the offset for that register configuration.) For example, if the bus number is 1000.0001 (0x81), the device number is 0.0000, and the function number is 001 (0x01), then use

ok " /pci@1f,2000" select-dev

ok 81.0100 config-l@ (to read device id and vendor id) ok 81.0104 config-w@ ( to read command register) ok 81.0130 config-l@ ( to read the expansion PROM base address register)

Boot Software Roles

There are three kinds of software that come into play during a boot:

• Operating system kernel,
• FCode operating system kernel driver.

This section describes the normal Solaris boot scenario, including their functions and the order in which they begin.

At power-on, the CPU PROM begins execution. It probes all on-board devices and plug-in cards to interpret the FCodes on all FCode PROMs. In the FCode probing process, some FCode PROMs execute commands to reset the device. But, generally, FCode PROMs generate device properties for respective devices.

Then, the CPU PROM boots over the specified boot device (using its FCode boot driver), loads bootblk (or inetboot for network booting), and passes control to the bootblk code. The bootblk code loads the kernel and modules, and passes control to the kernel. The kernel at some point starts to use the OS-device driver.

The order is:

• CPU-PROM
• FCode-PROM
• bootblk
• Operating system kernel
• Operating System driver

CPU PROM-Generated Properties

This section discusses the properties created by the motherboard CPU PROM from the information given in the configuration space registers of the PCI device.

The CPU PROM normally generates the following properties in a PCI device node:

• vendor-id
• device-id
• revision-id
• class-code

and devsel-speed from information in configuration space registers. The "interrupts" property is present if the Interrupt Pin register is non-zero. The following properties will be present only if the corresponding capability is available from the device or the corresponding value was non-zero as indicated in the configuration space registers:

• 66mhz-capable
• udf-supported
• cache-line-size
• fast-back-to-back
• subsystem-id
• subsystem-vendor-id

min-grant and max-latency properties are created unless the header type is 01. The CPU PROM also creates the "assigned-addresses" property, with entries for each address base register for which an address was assigned.