Table Notation

Table 5-1 shows the table notation used in this chapter to describe the instruction set of the assembler. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names.

Table 5-1

Notations	Describes	Comment
address	regrs1 + regrs2 regrs1 + const13 reg - const13 rs1 const13 + regrs1 const13	Address formed from register contents, immediate constant, or both.
asi		Alternate address space identifier; an unsigned 8-bit value. It can be the result of the evaluation of a symbol expression.
const13		A signed constant which fits in 13 bits. It can be the result of the evaluation of a symbol expression.
const22		A constant which fits in 22 bits. It can be the result of the evaluation of a symbol expression.
creg	%c0 ... %c31	Coprocessor registers.
freg	%f0 ... %f31	Floating-point registers.
imm7		A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 ... 127). It can be the result of the evaluation of a symbol expression.
reg	%r0 ... %r31 %g0 ... %g7 %o0 ... %o7 %l0 ... %l7 %i0 ... %i7	General purpose registers. Same as %r0 ... %r7 (Globals) Same as %r8 ... %r15 (Outs) Same as %r16 ... %r23 (Locals) Same as %r24 ... %r31 (Ins)
regrd		Destination register.
reg , reg rs1..rs2		Source register 1, source register 2.
reg_or_imm	reg , const13 rs2	Value from either a single register, or an immediate constant.

Table 5-1 (Continued)

Notations	Describes	Comment
regaddr	reg reg + reg rs1 rs1..rs2	Address formed with register contents only.
Software_trap_ number	regrs1 + regrs2 regrs1 + imm7 reg - imm7 rs1 uimm7 imm7 + regrs1	A value formed from register contents, immediate constant, or both. The resulting value must be in the range 0.....127, inclusive.
uimm7		An unsigned constant that can be represented in 7 bits (it is in the range 0 ... 127). It can be the result of the evaluation of a symbol expression.

Integer Instructions

The notations described in Table 5-2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names).

Table 5-2

Notation	Description
a	Instructions that deal with alternate space
b	Byte instructions
c	Reference to coprocessor registers
d	Doubleword instructions
f	Reference to floating-point registers
h	Halfword instructions
q	Quadword instructions
sr	Status register

Table 5-3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions.

The syntax of individual instructions is designed so that a destination operand (if any), which may be either a register or a reference to a memory location, is always the last operand in a statement.

---

Note - In Table 5-3,

• Braces ({ }) indicate optional arguments. Braces are not literally coded.
• Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to.

  Brackets are coded literally in the assembly language. Note that the usage of brackets described in Chapter 2, "Assembler Syntax" differs from the usage of these brackets.

• All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ",a" to the opcode mnemonic; for example,

"bgeu,a label"

Table 5-3 SPARC to Assembly Language Mapping

Opcode	Mnemonic	Argument List	Operation	Comments
ADD ADDcc ADDX ADDXcc	add addcc addx addxcc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Add Add and modify icc Add with carry
AND ANDcc ANDN ANDNcc	and andcc andn andncc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	And

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
BN	bn{,a}	label	Branch on integer condition	branch never
BNE BE	bne{,a} be{,a}	label label	codes	synonym: bnz synonym: bz
BG BLE BGE BI BGU BLEU BCC	bg{,a} ble{,a} bge{,a} bl{,a} bgu{,a} bleu{,a} bcc{,a}	label label label label label label label		synonym:
BCS	bcs{,a}	label		bgeu synonym: blu
BPOS BNEG BVC BVS BA	bpos{,a} bneg{,a} bvc{,a} bvs{,a} ba{,a}	label label label label label		synonym: b
CALL	call	label	Call subprogram
CBccc	cbn{,a} cb3{,a} cb2{,a} cb23{,a} cb1{,a} cb13{,eo} cb12{,a} cb123{,a} cb0{,a} cb03{,a} cb02{,a} cb023{,a} cb01{,a} cb013{,a} cb012{,a} cba{,a}	label label label label label label label label label label label label label label label label	Branch on coprocessor condition codes	branch never

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
FBN FBU FBG FBUG FBL FBUL FBLG FBNE	fbn{,a} fbu{,a} fbg{,a} fbug{,a} fbl{,a} fbul{,a} fblg{,a} fbne{,a}	label label label label label label label label	Branch on floating-point condition codes	branch never synonym:
FBE	fbe{,a}	label		fbnz synonym: fbz
FBUE FBGE FBUGE FBLE FBULE FBO FBA	fbue{,a} fbge{,a} fbuge{,a} fble{,a} fbule{,a} fbo{,a} fba{,a}	label label label label label label label
FLUSH	flush	address	Instruction cache flush
JMPL	jmpl	address, regrd	Jump and link
LDSB LDSH LDSTUB	ldsb ldsh ldstub	[address], regrd [address], regrd [address], reg	Load signed byte Load signed halfword Load-store unsigned byte
LDUB LDUH	ldub lduh	rd [address], regrd [address], regrd	Load unsigned byte Load unsigned halfword
LD	ld	[address], regrd	Load word
LDD	ldd	[address], reg	Load double word	reg must be
		rd		rd
LDF LDFSR	ld ld	[address], fregrd [address], %fsr	Load floating-point register	even
LDDF	ldd	[address], freg	Load double floating-point	freg must be
		rd		rd
			Load coprocessor	even
LDC LDCSR	ld ld	[address], cregrd [address], %csr	Load double coprocessor
LDDC	ldd	[address], cregrd

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
LDSBA	ldsba	[regaddr]asi, reg	Load signed byte from alternate
LDSHA LDUBA LDUHA LDA LDDA	ldsha lduba lduha lda ldda	rd [regaddr]asi, regrd [regaddr]asi, regrd [regaddr]asi, regrd [regaddr]asi, regrd [regaddr]asi, reg	space	reg must be
		rd		rd even
LDSTUBA	ldstuba	[regaddr]asi, regrd
MULScc	mulscc	reg , reg_or_imm, reg rs1......rd	Multiply step (and modify icc)
NOP	nop		No operation
OR ORcc ORN ORNcc	or orcc orn orncc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Inclusive or
RDASR RDY	rd rd	%asrn , reg rs1rd %y, reg			See synthetic
RDPSR	rd	rd %psr, regrd		instructions. See synthetic
RDWIM	rd	%wim, regrd		instructions. See synthetic
RDTBR	rd	%tbr, reg		instructions. See synthetic
		rd	instructions.
RESTORE	restore	reg , reg_or_imm, reg rs1......rd		See synthetic instructions.
RETT	rett	address	Return from trap
SAVE	save	reg , reg_or_imm, reg rs1......rd		See synthetic instructions.
SDIV SDIVcc	sdiv sdivcc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Signed divide Signed divide and modify icc

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
SMUL SMULcc	smul smulcc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Signed multiply Signed multiply and modify icc
SETHI	sethi	const22, reg	Set high 22 bits of register
	sethi	rd %hi(value), reg		See synthetic
		rd		instructions.
SLL SRL SRA	sll srl sra	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Shift left logical Shift right logical Shift right arithmetic
STB	stb	reg , [address	Store byte	Synonyms:
STH	sth	rd reg , [address] rd	Store half-word	stub, stsb Synonyms: stuh, stsh
ST STD STF	st std st	reg , [address] rd reg , [address] rd freg , [address]		reg Must be rd even
STDF STFSR	std st	rd freg , [address] rd %fsr, [address]	Store floating-point status	freg Must be
			register	rd even
STDFQ	std	%fq, [address]	Store double floating-point queue
STC STDC STCSR STDCQ	st std st std	creg , [address] rd creg , [address] rd %csr, [address]	Store coprocessor	creg Must be rd even
		%cq, [address]	Store double coprocessor
STBA	stba	reg [regaddr]asi	Store byte into alternate space	Synonyms:
STHA	stha	rd reg [regaddr]asi rd		stuba, stsba Synonyms: stuha, stsha
STA STDA	sta stda	reg , [regaddr]asi rd reg , [regaddr]asi		reg Must be
		rd		rd even

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
SUB SUBcc SUBX SUBXcc	sub subcc subx subxcc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Subtract Subtract and modify icc Subtract with carry
SWAP SWAPA	swap swapa	[address], regrd [regaddr]asi, regrd	Swap memory word with register
Ticc	tn	software_trap_number	Trap on integer condition code	Trap never
	tne	software_trap_number	Note: Trap numbers 16-31 are reserved for the user. Currently-defined trap numbers are those defined in /usr/include/sys/trap.h	Synonym: tnz
	te	software_trap_number		Synonym: tz
	tg tle tge tl tgu tleu	software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number		Synonym: tcs
	tlu	software_trap_number		Synonym: tcc
	tgeu	software_trap_number
	tpos tneg tvc	software_trap_number software_trap_number software_trap_number		Synonym: t
	tvs ta	software_trap_number software_trap_number
TADDcc	taddcc	reg , reg_or_imm, reg	Tagged add and modify icc
TSUBcc TADDccTV	tsubcc taddcctv	rs1......rd reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Tagged add and modify icc and trap on overflow
TSUBccTV	tsubcctv	reg , reg_or_imm, reg rs1......rd

Table 5-3 (Continued)

Opcode	Mnemonic	Argument List	Operation	Comments
UDIV UDIVcc	udiv udivcc	reg , reg_or_imm, reg rs1......rd reg , reg_or_imm, reg rs1......rd	Unsigned divide Unsigned divide and modify icc
UMUL	umul	reg , reg_or_imm, reg rs1.......rd	Unsigned multiply
UMULcc	umulcc	reg , reg_or_imm, reg rs1.......rd	Unsigned multiply and modify icc
UNIMP	unimp	const22	Illegal instruction
WRASR WRY	wr wr	reg_or_imm, %asrnrs1 reg , reg_or_imm, %y			See synthetic
WRPSR	wr	rs1 reg , reg_or_imm, %psr rs1		instructions See synthetic
		reg , reg_or_imm, %wim rs1		instructions
WRWIM	wr			See synthetic
WRTBR	wr	reg , reg_or_imm, %tbr rs1	instructions See synthetic instructions
XNOR XNORcc	xnor xnorcc	reg , reg_or_imm, reg rs1.......rd reg , reg_or_imm, reg rs1.......rd	Exclusive nor
XOR XORcc	xor xorcc	reg , reg_or_imm, reg rs1.......rd reg , reg_or_imm, reg rs1.......rd	Exclusive or

Floating-Point Instruction

Table 5-4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.

Table 5-4

SPARC	* Mnemonic	Argument List	Description
FiTOs FiTOd FiTOq	fitos fitod fitoq	freg , freg rs2 rd freg , freg rs2 rd freg , freg rs2 rd	Convert integer to single Convert integer to double Convert integer to quad
FsTOi FdTOi FqTOi	fstoi fdtoi fqtoi	freg , freg rs2 rd freg , freg rs2 rd freg , freg rs2 rd	Convert single to integer Convert double to integer Convert quad to integer
FsTOd FsTOq	fstod fstoq	freg , freg rs2 rd freg , freg rs2 rd	Convert single to double Convert single to quad
FdTOs FdTOq	fdtos fdtoq	freg , freg rs2 rd freg , freg rs2 rd	Convert double to single Convert double to quad
FqTOd FqTOs	fqtod fqtos	freg , freg rs2 rd freg , freg rs2 rd	Convert quad to double Convert quad to single
FMOVs FNEGs FABSs	fmovs fnegs fabss	freg , freg rs2 rd freg , freg rs2 rd freg , freg rs2 rd	Move Negate Absolute value
FSQRTs FSQRTd FSQRTq	fsqrts fsqrtd fsqrtq	freg , freg rs2 rd freg , freg rs2 rd freg , freg rs2 rd	Square root
FADDs FADDd FADDq	fadds faddd faddq	freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd	Add
* Types of Operands ar i integer s single d double q quad	e denoted by the following lower	-case letters:

Table 5-4 (Continued)

SPARC	* Mnemonic	Argument List	Description
FSUBs FSUBd FSUBq	fsubs fsubd fsubq	freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd	Subtract
FMULs FMULd FMULq	fmuls fmuld fmulq	freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd	Multiply
FdMULq FsMULd	fmulq fsmuld	freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd	Multiply double to quad Multiply single to double
FDIVs FDIVd FDIVq	fdivs fdivd fdivq	freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd freg , freg , freg rs1 rs2 rd	Divide
FCMPs FCMPd FCMPq FCMPEs	fcmps fcmpd fcmpq fcmpes	freg , freg rs1 rs2 freg , freg rs1 rs2 freg , freg rs1 rs2 freg , freg	Compare Compare, generate exception if
		rs1 rs2	not ordered
FCMPEd FCMPEq	fcmped fcmpeq	freg , freg rs1 rs2 freg , freg rs1 rs2
* Types of Operands ar i integer s single d double q quad	e denoted by the following lower	-case letters:

Coprocessor Instructions

All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. The data types supported by the coprocessor are coprocessor-dependent. Operand alignment is also coprocessor-dependent. Coprocessor-operate instructions are described in Table 5-5.

If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0, or if a coprocessor is not present, a cpopn instruction causes a cp_disabled trap.

The conditions that cause a cp_exception trap are coprocessor-dependent. Table 5-5

Coprocessor-Operate Instructions

SPARC	Mnemonic	Argument List	Name	Comments
CPop1	cpop1	opc, reg , reg , reg rs1rs2rd	Coprocessor operation
CPop2	cpop2	opc, reg , reg , reg rs1rs2rd	Coprocessor operation	May modify ccc

Synthetic Instructions

Table 5-6 describes the mapping of synthetic instructions to hardware instructions.

Table 5-6

Synthetic Instruction		Hardware Equivalent(s)		Comment
btst bset bclr btog	reg_or_imm, regrs1 reg_or_imm, regrd reg_or_imm, regrd reg_or_imm, regrd	andcc or andn xor	reg , reg_or_imm, %g0 rs1 reg , reg_or_imm, reg rd......rd reg , reg_or_imm, reg rd......rd reg , reg_or_imm, reg rd......rd	Bit test Bit set Bit clear Bit toggle
call	reg_or_imm	jmpl	reg_or_imm, %o7
clr clrb clrh clr	regrd [address] [address] [address]	or stb sth st	%g0, %g0, regrd %g0, [address] %g0, [address] %g0, [address]	Clear (zero) register Clear byte Clear halfword Clear word
cmp	reg, reg_or_imm	subcc	reg , reg_or_imm, %g0 rs1	Compare
dec dec deccc	regrd const13, regrd reg	sub sub subcc	reg , 1, reg rd rd reg , const13, reg rd....rd reg , 1, reg	Decrement by 1 Decrement by const13 Decrement by 1
deccc	rd const13, reg	subcc	rd rd reg , const13, reg	and set icc Decrement by
	rd		rd....rd	const13 and set icc

Table 5-6 (Continued)

Synthetic Instruction		Hardware Equivalent(s)		Comment
inc inc inccc	regrd const13, regrd reg	add add addcc	reg , 1, reg rd rd reg , const13, reg rd....rd reg , 1, reg	Increment by 1 Increment by const13 Increment by 1
inccc	rd const13, reg	addcc	rd rd reg , const13, reg	and set icc Increment by
	rd		rd....rd	const13 and set icc
jmp	address	jmpl	address, %g0
mov mov mov mov mov mov mov mov mov	reg_or_imm,regrd %y, regrs1 %psr, regrs1 %wim, regrs1 %tbr, regrs1 reg_or_imm, %y reg_or_imm, %psr reg_or_imm, %wim reg_or_imm, %tbr	or rd rd rd rd wr wr wr wr	%g0, reg_or_imm, regrd %y, regrs1 %psr, regrs1 %wim, regrs1 %tbr, regrs1 %g0,reg_or_imm,%y %g0,reg_or_imm,%psr %g0,reg_or_imm,%wim %g0,reg_or_imm,%tbr
not not neg neg	reg , reg rs1rd regrd reg , reg rs1rd regrd	xnor xnor sub sub	reg , %g0, reg rs1...rd reg , %g0, reg rd...rd %g0, reg , reg rs2rd %g0, reg , reg rdrd	One's complement One's complement Two's complement Two's complement
restore		restore	%g0, %g0, %g0	Trivial restore
save		save	%g0, %g0, %g0	Trivial save trivial save should only be used in supervisor code!
set set set	value,regrd value,regrd value,regrd	or sethi sethi or	%g0, value, regrd %hi(value), regrd %hi(value), reg ; rd reg , %lo(value), reg rd......rd	if -4096 . value . 4095 if ((value & 0x3ff) == 0) otherwise Do not use the set synthetic instruction in an instruction delay slot.

Table 5-6 (Continued)

Synthetic Instruction		Hardware Equivalent(s)		Comment
skipz skipnz		bnz,a .+8 bz,a .+8		if z is set, ignores next instruction if z is not set, ignores next instruction
tst	reg	orcc	reg , %g0, %g0 rs1	test