3.1 Introduction

This chapter describes the instruction set mappings for the SunOS x86 processor. For more details of the operation and a summary of the exceptions, please refer to the i486 Microprocessor Programmer's Reference Manual from Intel Corporation.

Although the Intel processor supports address-size attributes of either 16 or 32 bits, the x86 assembler only supports address-size attributes of 32 bits. The operand-size is either 16 or 32 bits. An instruction that accesses 16-bit words or 32-bit longs has an operand-size attribute of either 16 or 32 bits.

Notational Conventions

The notational conventions used in the instructions included in this chapter are described below:

• The mnemonics are expressed in a regular expression-type syntax.
• When a group of letters is separated from other letters by a bar (|) within square brackets or curly braces, then the group of letters between the bars or between a bar and a closing bracket or brace is considered an atomic unit.

  For example, fld[lst] means fldl, flds, or fldt; fst{ls} means fst, fstl, or fsts; and fild{l|ll} means fild, fildl, or fildll.

• Square brackets ([]) denotes choices, but at least one irequired. .

. Alternatives enclosed within curly braces ({}) denote that you can use one or none of them

. The vertical bar separates different suffixes for operators or operands. For example, the following indicates that an 8-, 16-, or 32-bit immediate value is permitted in an instruction:

imm[8|16|32]

• The SunOS operators are built from the Intel operators by adding suffixes to them. The 80387, 80486 deals with three data types: integer, packed decimal, and real.

  The SunOS assembler is not typed; the operator has to carry with it the type of data item it is operating on. If the operation is on an integer, the following suffixes apply: none for Intel's short(16 bits), l for Intel's long (32 bits), and ll for Intel's longlong(64 bits). If the operator applies to reals, then: s is short (32 bits), l is long (64 bits), and t is temporary real(80 bits).

• reg[8|16|32] defines a general-purpose register, where each number indicates one of the following:

32:%eax, %ecx, %edx, %ebx, %esi, %edi, %ebp, %esp

16:%ax, %cx, %dx, %bx, %si, %di, %bp, %sp

8: %al, %ah, %cl, %ch, %dl, %dh, %bl, %bh

• mem[8|16|32|48]stands for a memory operand, which is one of the following: the 8, 16, 32, and 48 suffixes represent byte, word, long, and inter-segment memory address quantities, respectively.
• r/m[8|16|32] is a general-purpose register or memory operand; the operand type is determined from the suffix. They are: 8 = byte, 16 = word, and 32 = long. The registers for each operand size are the same as reg[8|16|32] above.
• creg is a control register; the control registers are: %cr0, %cr2, or %cr3.
• dreg is a debug register; the debug registers are: %db0, %db1, %db2, %db3, %db6, %db7.
• sreg is a segment register. The segment registers are: %cs, %ds, %ss, %es, %fs, and %gs.
• treg is a test register. The test registers are: %tr6 and %tr7.
• .freg is floating point registers %st, %st(1) - %st(7).

• cc represent condition codes. There are 30 condition codes. For more information on condition codes, refer to Chapter 2, "Assembler Input," in this manual.

References

This document presumes that you are familiar with the manner in which the Intel instruction sets function. For more information on specific instruction descriptions, please refer to x86 product documentation from Intel Corporation.

3.2 Segment Register Instructions

Following are the segment register instructions supported by the x86 processor.

Load Full Pointer (lds, les, lfs, lgs, and lss)

lds{wl}          mem[32|48], reg[16|32]
les{wl}          mem[32|48], reg[16|32]
lfs{wl}          mem[32|48], reg[16|32]
lgs{wl}          mem[32|48], reg[16|32]
lss{wl}          mem[32|48], reg[16|32]

Pop Stack into Word (pop)

pop{wl}    r/m[16|32]
pop{l}     [%ds|%ss|%es|%fs|%gs]

Push Stack into Word(push)

push{wl}   r/m[16|32]
push{wl}   imm[8|16|32]
push{l}    [%cs|%ds|%ss|%es|%fs|%gs]

3.3 I/O Instructions

Input from Port (in, ins)

in{bwl}   imm8
in{bwl}   (%dx)
ins{bwl}

Output from Port (out, outs)

out{bwl} imm8
out{bwl} (%dx)
outs{bwl}

3.4 Flag Instructions

Load Flags into AH Register (lahf)

lahf

Store AH into Flags (sahf)

sahf

Pop Stack into Flag (popf)

popf{wl}

Push Stack into Flag (pushf)

pushf{wl}

Complement Carry Flag (cmc)

cmc

Clear Carry Flag (clc)

clc

Set Carry Flag (stc)

stc

Clear Interrupt Flag (cli)

cli

Set Interrupt Flag (sti)

sti

Clear Direction Flag (cld)

cld

Set Direction Flag (std)

std

3.5 Arithmetic Logical Instructions

Integer Addition (add)

add{bwl} reg[8|16|32], r/m[8|16|32]
add{bwl} r/m[8|16|32], reg[8|16|32]
add{bwl} imm[8|16|32], r/m[8|16|32]

Integer Add With Carry (adc)

adc{bwl} reg[8|16|32], r/m[8|16|32]
adc{bwl} r/m[8|16|32], reg[8|16|32]
adc{bwl} imm[8|16|32], r/m[8|16|32]

Integer Subtraction (sub)

sub{bwl} reg[8|16|32], r/m[8|16|32]
sub{bwl} r/m[8|16|32], reg[8|16|32]
sub{bwl} imm[8|16|32], r/m[8|16|32]

Integer Subtraction With Borrow (sbb)

sbb{bwl} reg[8|16|32], r/m[8|16|32]
sbb{bwl} r/m[8|16|32], reg[8|16|32]
sbb{bwl} imm[8|16|32], r/m[8|16|32]

Compare Two Operands (cmp)

cmp{bwl}     reg[8|16|32], r/m[8|16|32]
cmp{bwl}     r/m[8|16|32], reg[8|16|32]
cmp{bwl}     imm[8|16|32], r/m[8|16|32]

Increment by 1 (inc)

inc{bwl}     r/m[8|16|32]

Decrease by 1 (dec)

dec{bwl}     r/m[8|16|32]

Logical Comparison or Test (test)

test{bwl}    reg[8|16|32], r/m[8|16|32]
test{bwl}    r/m[8|16|32], reg[8|16|32]
test{bwl}    imm[8|16|32], r/m[8|16|32]

Shift (sal, shl, sar, shr)

sal{bwl} imm8, r/m[8|16|32]
sal{bwl} %cl, r/m[8|16|32]
shl{bwl} imm8, r/m[8|16|32]
shl{bwl} %cl, r/m[8|16|32]

sar{bwl} imm8, r/m[8|16|32]
sar{bwl} %cl, r/m[8|16|32]
shr{bwl} imm8, r/m[8|16|32]
shr{bwl} %cl, r/m[8|16|32]

Double Precision Shift Left (shld)

shld{wl} imm8, reg[16|32], r/m[16,32]
shld{wl} reg[16|32], r/m[16,32], r/m[16,32]

Double Precision Shift Right (shrd)

shrd{wl} imm8, reg[16|32]
shrd{wl} reg[16|32], r/m[16,32]

One's Complement Negation (not)

not{bwl}      r/m[8|16|32]

Two's Complement Negation (neg)

neg{bwl}      r/m[8|16|32]

Check Array Index Against Bounds (bound)

bound{wl}     r/m[16|32], reg[16|32]

Logical And (and)

and{bwl} reg[8|16|32], r/m[8|16|32]
and{bwl} r/m[8|16|32], reg[8|16|32]
and{bwl} imm[8|16|32], r/m[8|16|32]

Logical Inclusive OR (or)

or{bwl}   reg[8|16|32], r/m[8|16|32]
or{bwl}   r/m[8|16|32], reg[8|16|32]

or{bwl}   imm[8|16|32], r/m[8|16|32]

Logical Exclusion OR (xor)

xor{bwl} reg[8|16|32], r/m[8|16|32]
xor{bwl} r/m[8|16|32], reg[8|16|32]
xor{bwl} imm[8|16|32], r/m[8|16|32]

3.6 Multiply and Divide Instructions

When the type suffix is not included in a multiply or divide instruction, it defaults to a long.

Signed Multiply (imul)

imulb       r/m8
imulw       r/m16
imul{l}     r/m32
imul{wl}    r/m[16|32], reg[16|32]
imul{bwl}   imm[16|32], r/m[16|32], reg[16|32]

Unsigned Multiplication of AL, AX or EAX(mul)

mul{bwl} r/m[8|16|32]

Unsigned Divide (div)

div{bwl}         r/m[8|16|32]

Signed Divide (idiv)

idiv{bwl}        r/m[8|16|32]

3.7 Conversion Instructions

Convert Byte to Word (cbtw)

cbtw

Convert Word to Long (cwtl)

  cwtl

Convert Signed Word to Signed Double Word (cwtd)

  cwtd

Convert Signed Long to Signed Double Long (cltd)

cltd

3.8 Decimal Arithmetic Instructions

Decimal Adjust AL after Addition (daa)

daa

Decimal Adjust AL after Subtraction (das)

das

ASCII Adjust after Addition (aaa)

aaa

ASCII Adjust after Subtraction (aas)

aas

ASCII Adjust AX after Multiply (aam)

aam

ASCII Adjust AX before Division (aad)

aad

3.9 Coprocessor Instructions

Wait (wait, fwait)

wait
fwait

3.10 String Instructions

All Intel string op mnemonics default to long.

Move Data from String to String (movs, smov)

movs{bwl}
smov{bwl}

Compare String Operands (cmps, scmp)

cmps{bwl}
scmp{bwl}

Store String Data (stos, ssto)

stos{bwl}
ssto{bwl}

The Load String Operand (lods, slod)

lods{bwl}
slod{bwl}

Compare String Data (scas, ssca)

scas{bwl}
ssca{bwl}

Look-Up Translation Table (xlat)

xlat

Repeat Following String Operation (rep, repnz, repz)

rep
repnz
repz

3.11 Procedure Call and Return Instructions

lcall    immptr
lcall    *mem48

Call Procedure (call)

call     disp32
call     *r/m32

Return from Procedure (ret)

ret
ret      imm16

Long Return (lret)

lret
lret     imm16

Enter or Make a Stack Frame for Procedure Parameters (enter)

enter    imm16, imm8

High Level Procedure Exit (leave)

leave

3.12 Jump Instructions

Jump if ECX is Zero (jcxz)

jcxz     disp8

Loop Control with CX Counter (loop, loopnz, loopz)

loop     disp8
loopnz   disp8
loopne   disp8
loopz    disp8
loope   disp8

Jump (jmp, ljmp)

jmp        disp[8|32]
ljmp       immPtr
jmp        *r/m32
ljmp       *mem48
jcc         disp[8|32]

3.13 Interrupt Instructions

Call to Interrupt Procedure (int, into)

int      imm8
into

Interrupt Return (iret)

iret

3.14 Protection Model Instructions

Store Local Descriptor Table Register (sldt)

sldt     r/m16

Store Task Register (str)

str      r/m16

Load Local Descriptor Table Register (lldt)

lldt     r/m16

Load Task Register (ltr)

ltr      r/m16

Verify a Segment for Reading or Writing (verr, verw)

verr     r/m16
verw     r/m16

Store Global/Interrupt Descriptor Table Register (sgdt, sidt)

sgdt     mem48
sidt     mem48

Load Global/Interrupt Descriptor Table (lgdt, lidt)

lgdt     mem48
lidt     mem48

Store Machine Status Word (smsw)

smsw     r/m16

Load Machine Status Word (lmsw)

lmsw     r/m16

Load Access Rights (lar)

   lar      r/m32, reg32

Load Segment Limit (lsl)

lsl      r/m32, reg32

Clear Task-Switched (clts)

clts

Adjust RPL Field of Selector (arpl)

arpl r16, r/m16

3.15 Bit Instructions

Bit Scan Forward

bsf{wl}      r/m[16|32], reg[16|32]

Bit Scan Reverse

bsr{wl}      r/m[16|32], reg[16|32]

Bit Test

bt{wl}       imm8, r/m[16|32]
bt{wl}       reg[16|32], r/m[16|32]

Bit Test And Complement

btc{wl}      imm8, r/m[16|32]
btc{wl}      reg[16|32], r/m[16|32]

Bit Test And Reset

btr{wl}      imm8, r/m[16|32]
btr{wl}      reg[16|32], r/m[16|32]

Bit Test And Set

bts{wl}      imm8, r/m[16|32]
bts{wl}      reg[16|32], r/m[16|32]

3.16 Exchange Instructions

Compare and Exchange [486]

cmpxchg{bwl}  reg[8|16|32], r/m[8|16|32]

3.17 Floating Point Transcendental

Floating Point Sine

fsin

Floating Point Cosine

fcos

Floating Point Sine and Cosine

fsincos

3.18 Floating Point Constant

Floating Point Load One

fld1
fld12+
fld12e

fldpi
fldlg2
fldln2
fldz

3.19 Processor Control Floating Point

Floating Point Load Control Word

fldcw        r/m16

Floating Point Load Environment

fldenv       mem

3.20 Other Floating Point

Floating Point Different Reminder

fprem1

3.21 Floating Point Comparison

Floating Point Unsigned Compare

fucom        freg

Floating Point Unsigned Compare And Pop

fucomp       freg

Floating Point Unsigned Compare And Pop Two

fucompp

3.22 Load and Move Instructions

Load Effective Address

lea{wl}      r/m[16|32], reg[16|32]

Move

mov{bwl}     imm[8|16|32], r/m[8|16|32]
mov{bwl}     reg[8|16|32], r/m[8|16|32]
mov{bwl}     r/m[8|16|32], reg[8|16|32]

Move Segment Registers

movw       sreg,r/m16
movw       r/m16, sreg

Move Control Registers

mov{l}       creg, reg32
mov{l}       reg32, creg

Move Debug Registers

mov{l}       dreg, reg32
mov{l}       reg32, dreg

Move Test Registers

mov{l}       treg, reg32
mov{l}       reg32, treg

Move With Sign Extend

movsb{wl}     r/m8, reg[16|32]
movsbwl       r/m16, reg32

Move With Zero Extend

movzb[wl]    r/m8, reg[16|32]
movzwl       r/m16, reg32

3.23 Pop Instructions

Pop All General Registers

popa{wl}

3.24 Push Instructions

Push All General Registers

pusha{wl}

3.25 Rotate Instructions

Rotate With Carry Left

rcl{bwl}     imm8, r/m[8|16|32]
rcl{bwl}     %cl, r/m[8|16|32]

Rotate With Carry Right

rcr{bwl}     imm8, r/m[8|16|32]
rcr{bwl}     %cl, r/m[8|16|32]

Rotate Left

rol{bwl}     imm8, r/m[8|16|32]
rol{bwl}     %cl, r/m[8|16|32]

Rotate Right

ror{bwl}     imm8, r/m[8|16|32]

ror{bwl}     %cl, r/m[8|16|32]

3.26 Byte Instructions

Byte Set On Condition

setcc        r/m8

Byte Swap [486]

bswap        reg[16|32]

3.27 Exchange Instructions

Exchange And Add [486]

xadd{bwl}    reg[8|16|32], r/m[8|16|32]

Exchange Register / Memory With Register

xchg{bwl}    reg[8|16|32], r/m[8|16|32]

3.28 Miscellaneous Instructions

Write Back and Invalidate Cache [486 only]

wbinvd

Invalidate [486 only]

invd

Invalidate Page [486 only]

invlpg       mem32

LOCK Prefix (lock)

lock

No Operation (nop)

nop

Halt (hlt)

hlt
Address Prefix
addr16
Data Prefix
data16

3.29 Real Transfers

Load real

fld{lst}

Store real

fst{ls}

Store real and pop

fstp{lst}

Exchange registers

fxch

3.30 Integer Transfers

Integer load

fild{l|ll}

Integer store

fist{l}

Integer store and pop

fistp{l|ll}

3.31 Packed Decimal Transfers

Packed decimal (BCD) load

fbld

Packed decimal (BCD) store and pop

fbstp

3.32 Additions

Real add

fadd{ls}

Real add and pop

faddp

Integer add

fiadd{l}

3.33 Subtractions

Subtract real and pop

fsub{ls}

Subtract real

subp

Subtract real reversed

fsubr{ls}

Subtract real reversed and pop

fsubrp

Integer subtract

fsubrp

Integer subtract reverse

fisubr{l}

3.34 Multiplications

Multiply real

fmul{ls}

Multiply real and pop

fmulp

Integer multiply

fimul{l}

3.35 Divisions

Divide real

fdiv{ls}

Divide real and pop

divp

Divide real reversed

fdivr{ls}

Divide real reversed and pop

fdivrp

Integer divide

fidiv{l}

Integer divide reversed

fidivr{l}

3.36 Floating Point Opcode Errors

---

Warning - The SunOS x86 assembler generates the wrong object code for some of the floating point opcodes fsub, fsubr, fdiv, and fdivr when there are two floating register operands, and the second op destination is not the zeroth floating point register. This error has been made to many versions of the USL UNIX^(R) system and would probably cause problems if it were fixed.

---

Replace the following instructions, in column 1, with their substitutions, in column 2, for x86 platforms:

fsub %st,%st(n)                        fsubr %st, %st(n)
fsubp %st,%st(n)                       fsubrp %st, %st(n)
fsub                                   fsubr
fsubr %st,%st(n)                       fsub %st, %st(n)
fsubrp %st,%st(n)                      fsubp %st, %st(n)
fsubr                                  fsub
fdiv %st,%st(n)                        fdivr %st,%st(n)
fdivp %st,%st(n)                       fdivrp %st,%st(n)
fdiv                                   fdivr
fdivr %st,%st(n)                       fdiv %st,%st(n)
fdivrp %st,%st(n)                      fdivp %st,%st(n)
fdivr                                  fdiv

3.37 Other Arithmetic Operations

Square root

fsqrt

Scale

fscale

Partial remainder

fprem

Round to integer

frndint

Extract exponent and significand

fxtract

Absolute value

fabs

Change sign

fchs

3.38 Comparison Instructions

Compare real

fcom{ls}

Compare real and pop

fcomp{ls}

Compare real and pop twice

fcompp

Integer compare

ficom{l}

Integer compare and pop

ficomp{l}

Test

ftst

Examine

fxam

3.39 Transcendental Instructions

Partial tangent

fptan

Partial arctangent

fptan

2

x - 1

f2xm1

Y * log2 X

fyl2x

Y * log

(X+1) 2

fyl2xp1

3.40 Constant Instructions

Load log

E 2

fldl2e

Load log

10 2

fldl2t

Load log

2 10

fldlg2

Load log

2 e

fldln2

Load pi

fldpi

Load + 0

fldz

3.41 Processor Control Instructions

Initialize processor

finit/fninit

No operation

fnop

Save state

fsave/fnsave

Store control word

fstcw/fnstcw

Store environment

fstenv/fnstenv

Store status word

fstsw/fnstsw

Restore state

frstor

Set protected mode

fsetpm

CPU wait

fwait/wait

Clear exceptions

fclex/fnclex

Decrement stack pointer

fdecstp

Free registers

ffree

Increment stack pointer

fincstp