Table Notation

Table 5-1 describes the notation used in the tables in this chapter to describe the instruction set of the assembler. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names):

Table 5-1

Notations	Describes	Comment
address	regrs1 + regrs2 regrs1 + const13 reg - const13 rs1 const13 + regrs1 const13	Address formed from register contents, immediate constant, or both.
asi		Alternate address space identifier; an unsigned 8-bit value. It can be the result of the evaluation of a symbol expression.
const13		A signed constant which fits in 13 bits. It can be the result of the evaluation of a symbol expression.
const22		A constant which fits in 22 bits. It can be the result of the evaluation of a symbol expression.
creg	%c0 ... %c31	Coprocessor registers.
freg	%f0 ... %f31	Floating-point registers.
imm7		A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 ... 127). It can be the result of the evaluation of a symbol expression.
reg	%r0 ... %r31	General purpose registers.
	%g0 ... %g7	Same as %r0 ... %r7 (Globals)
	%o0 ... %o7	Same as %r8 ... %r15 (Outs)
	%l0 ... %l7	Same as %r16 ... %r23 (Locals)
	%i0 ... %i7	Same as %r24 ... %r31 (Ins)
regrd		Destination register.
reg , reg rs1..rs2		Source register 1, source register 2.

Table 5-1

Notations	Describes	Comment
reg_or_imm	regrs2 const13	Value from either a single register, or an immediate constant.
regaddr	regrs1 reg + reg rs1...rs2	Address formed with register contents only.
Software_trap_number	regrs1 + regrs2 regrs1 + imm7 reg - imm7 rs1 uimm7 imm7 + regrs1	A value formed from register contents, immediate constant, or both. The resulting value must be in the range 0.....127, inclusive.
uimm7		An unsigned constant that can be represented in 7 bits (it is in the range 0 ... 127). It can be the result of the evaluation of a symbol expression.

Integer Instructions

The notations described in Table 5-2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names).

Table 5-2

Notation	Description
a	Instructions that deal with alternate space
b	Byte instructions
c	Reference to coprocessor registers
d	Doubleword instructions
f	Reference to floating-point registers
h	Halfword instructions
q	Quadword instructions
sr	Status register

Table 5-3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions.

The syntax of individual instructions is designed so that a destination operand (if any), which may be either a register or a reference to a memory location, is always the last operand in a statement.

---

Note - In Table 5-3,

• Braces ({ }) indicate optional arguments. Braces are not literally coded.
• Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to.

  Brackets are coded literally in the assembly language. Note that the usage of brackets described in Chapter 2, "Assembler Syntax" differ from the usage of these brackets.

• All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ",a" to the opcode mnemonic; for example,

     "bgeu,a label"



Table 5-3SPARC to Assembly Language Mapping

SPARC	Mnemonic	Argument List	Name	Comments
ADD	add	reg , reg_or_imm, reg	Add
ADDcc	addcc	rs1..........rd reg , reg_or_imm, reg	Add and modify icc
ADDX	addx	rs1..........rd reg , reg_or_imm, reg	Add with carry
ADDXcc	addxcc	rs1..........rd reg , reg_or_imm, reg rs1..........rd
AND	and	reg , reg_or_imm, reg	And
ANDcc	andcc	rs1..........rd reg , reg_or_imm, reg
ANDN	andn	rs1..........rd reg , reg_or_imm, reg
ANDNcc	andncc	rs1..........rd reg , reg_or_imm, reg rs1..........rd

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
Bicc	bn{,a}	label	Branch on integer	branch never
	bne{,a}	label	condition codes	synonym: bnz
	be{,a}	label		synonym: bz
	bg{,a}	label
	ble{,a}	label
	bge{,a}	label
	bl{,a}	label
	bgu{,a}	label
	bleu{,a}	label
	bcc{,a}	label		synonym: bgeu synonym: blu
	bcs{,a}	label
	bpos{,a}	label
	bneg{,a}	label
	bvc{,a}	label
	bvs{,a}	label		synonym: b
	ba{,a}	label
CALL	call	label label{,n}	Call subprogram	n = # of out registers used as arguments

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
CBccc	cbn{,a} cb3{,a}	label label	Branch on coprocessor	branch never
	cb2{,a}	label	condition codes
	cb23{,a}	label
	cb1{,a}	label
	cb13{,eo } cb12{,a}	label label label
	cb123{,a } cb0{,a} cb03{,a} cb02{,a}	label label label label label
	cb023{,a } cb01{,a} cb013{,a } cb012{,a } cba{,a}	label label label

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
FBfcc	fbn{,a}	label	Branch on	branch never
	fbu{,a}	label	floating-point
	fbg{,a}	label	condition codes
	fbug{,a}	label
	fbl{,a}	label
	fbul{,a}	label
	fblg{,a}	label
	fbne{,a}	label		synonym: fbnz
	fbe{,a}	label		synonym: fbz
	fbue{,a}	label
	fbge{,a}	label
	fbuge{,a } fble{,a}	label label label
	fbule{,a } fbo{,a} fba{,a}	label label
FLUSH	flush	address	Instruction cache flush
JMPL	jmpl	address, regrd	Jump and link

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
LDSB	ldsb	[address], reg	Load signed byte
LDSH	ldsh	rd [address], reg	Load signed halfword
LDSTUB	ldstub	rd [address], reg	Load-store unsigned
		rd	byte Load unsigned byte
LDUB	ldub	[address], reg
LDUH	lduh	rd [address], regrd	Load unsigned halfword
LD	ld	[address], regrd	Load word
LDD	ldd	[address], regrd	Load double word	reg must be rd
LDF	ld	[address], freg		even
LDFSR	ld	rd [address], %fsr	Load floating-point register
LDDF	ldd	[address], fregrd
			Load double floating-point	freg must be rd even
LDC	ld	[address], creg	Load coprocessor
LDCSR	ld	rd [address], %csr
LDDC	ldd	[address], cregrd	Load double coprocessor
LDSBA	ldsba	[regaddr]asi, reg	Load signed byte
LDSHA	ldsha	rd [regaddr]asi, reg	from alternate space
LDUBA	lduba	rd [regaddr]asi, reg
LDUHA	lduha	rd [regaddr]asi, reg
LDA	lda	rd [regaddr]asi, reg
LDDA	ldda	rd [regaddr]asi, reg		reg must be
		rd		rd even
LDSTUBA	ldstuba	[regaddr]asi, regrd

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
MULScc	mulscc	reg , reg_or_imm, reg rs1..........rd	Multiply step (and modify icc)
NOP	nop		No operation
OR	or	reg , reg_or_imm, reg	Inclusive or
ORcc	orcc	rs1..........rd reg , reg_or_imm, reg
ORN	orn	rs1..........rd reg , reg_or_imm, reg
ORNcc	orncc	rs1..........rd reg , reg_or_imm, reg rs1..........rd
RDASR	rd	%asrn , reg		1.n.31
RDY	rd	rs1..rd %y, reg		See synthetic
		rd		instructions
RDPSR	rd	%psr, regrd		See synthetic instructions
RDWIM	rd	%wim, regrd		See synthetic instructions
RDTBR	rd	%tbr, regrd		See synthetic instructions
RESTORE	restore	reg , reg_or_imm, reg rs1...........rd		See synthetic instructions
RETT	rett	address	Return from trap
SAVE	save	reg , reg_or_imm, reg rs1..........rd		See synthetic instructions
SDIV	sdiv	reg , reg_or_imm, reg	Signed divide
SDIVcc	sdivcc	rs1..........rd reg , reg_or_imm, reg rs1..........rd	Signed divide and modify icc

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
SMUL	smul	reg , reg_or_imm, reg	Signed multiply
SMULcc	smulcc	rs1..........rd reg , reg_or_imm, reg rs1..........rd	Signed multiply and modify icc
SETHI	sethi	const22, reg	Set high 22 bits of
	sethi	rd %hi(value), reg	register	See synthetic
		rd		instructions
SLL	sll	reg , reg_or_imm, reg	Shift left logical
SRL	srl	rs1..........rd reg , reg_or_imm, reg	Shift right logical
SRA	sra	rs1..........rd reg , reg_or_imm, reg rs1..........rd	Shift right arithmetic
STB	stb	reg , [address]	Store byte	Synonyms:
STH	sth	rd reg , [address] rd	Store half-word	stub, stsb Synonyms: stuh, stsh
ST	st	reg , [address] rd
STD	std	reg , [address]		reg Must be even
		rd		rd
STF	st	freg , [address] rd
STDF	std	freg , [address]		freg Must be even
		rd		rd
STFSR	st	%fsr, [address]	Store floating-point status register
STDFQ	std	%fq, [address]	Store double floating-point
STC	st	creg , [address] rd	Store coprocessor
STDC	std	creg , [address]		creg Must be even
STCSR	st	rd %csr, [address]		rd
STDCQ	std	%cq, [address]	Store double coprocessor

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
STBA	stba	reg [regaddr]asi	Store byte into	Synonyms:
STHA	stha	rd reg [regaddr]asi rd	alternate space	stuba, stsba Synonyms: stuha, stsha
STA	sta	reg , [regaddr]asi rd
STDA	stda	reg , [regaddr]asi rd		reg Must be even rd
SUB	sub	reg , reg_or_imm, reg	Subtract
SUBcc	subcc	rs1..........rd reg , reg_or_imm, reg	Subtract and modify
		rs1..........rd	icc
SUBX	subx	reg , reg_or_imm, reg
		rs1..........rd	Subtract with carry
SUBXcc	subxcc	reg , reg_or_imm, reg rs1..........rd
SWAP	swap	[address], reg	Swap memory word
SWAPA	swapa	rd [regaddr]asi, regrd	with register

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
Ticc	tn	software_trap_number	Trap on integer	Trap never
	tne	software_trap_number	condition code Note: Trap numbers	Synonym:
			16-31 are reserved for the user. Currently-defined trap numbers are those defined in /usr/include/sys/trap.h	tnz Synonym: tz
	te	software_trap_number
	tg	software_trap_number
	tle	software_trap_number
	tge	software_trap_number
	tl	software_trap_number
	tgu	software_trap_number
	tleu	software_trap_number
	tlu	software_trap_number		Synonym: tcs
	tgeu	software_trap_number		Synonym: tcc
	tpos	software_trap_number
	tneg	software_trap_number
	tvc	software_trap_number
	tvs	software_trap_number
	ta	software_trap_number		Synonym: t

Table 5-3 (Continued)

SPARC	Mnemonic	Argument List	Name	Comments
TADDcc	taddcc	reg , reg_or_imm, reg	Tagged add and
TSUBcc	tsubcc	rs1..........rd reg , reg_or_imm, reg	modify icc
TADDccT	taddcctv	rs1..........rd reg , reg_or_imm, reg rs1..........rd	Tagged add and
V			modify icc and trap on overflow
TSUBccT V	tsubcctv	reg , reg_or_imm, reg rs1..........rd
UDIV	udiv	reg , reg_or_imm, reg	Unsigned divide
UDIVcc	udivcc	rs1..........rd reg , reg_or_imm, reg rs1..........rd	Unsigned divide and modify icc
UMUL	umul	reg , reg_or_imm, reg rs1............rd	Unsigned multiply
UMULcc	umulcc	reg , reg_or_imm, reg rs1............rd	Unsigned multiply and modify icc
UNIMP	unimp	const22	Illegal instruction
WRASR	wr	reg_or_imm, %asrn		1.n.31
WRY	wr	rs1 reg , reg_or_imm, %y		See synthetic
		rs1		instructions
WRPSR	wr	reg , reg_or_imm, %psr rs1		See synthetic instructions
WRWIM	wr	reg , reg_or_imm, %wim rs1		See synthetic instructions
WRTBR	wr	reg , reg_or_imm, %tbr rs1		See synthetic instructions
XNOR	xnor	reg , reg_or_imm, reg	Exclusive nor
XNORcc	xnorcc	rs1............rd reg , reg_or_imm, reg rs1............rd
XOR	xor	reg , reg_or_imm, reg	Exclusive or
XORcc	xorcc	rs1............rd reg , reg_or_imm, reg rs1............rd

Floating-Point Instruction

Table 5-4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.

Table 5-4

SPARC	* Mnemonic	Argument List	Description
FiTOs	fitos	freg , freg	Convert integer to single
FiTOd		rs2...rd
	fitod	freg , freg	Convert integer to double
FiTOq		rs2...rd
	fitoq	freg , freg rs2...rd	Convert integer to quad
FsTOi	fstoi	freg , freg	Convert single to integer
FdTOi		rs2...rd
	fdtoi	freg , freg	Convert double to integer
FqTOi		rs2...rd
	fqtoi	freg , freg rs2...rd	Convert quad to integer
FsTOd	fstod	freg , freg	Convert single to double
FsTOq		rs2...rd
	fstoq	freg , freg rs2...rd	Convert single to quad
FdTOs	fdtos	freg , freg	Convert double to single
FdTOq		rs2...rd
	fdtoq	freg , freg rs2...rd	Convert double to quad
FqTOd	fqtod	freg , freg	Convert quad to double
FqTOs		rs2...rd
	fqtos	freg , freg rs2...rd	Convert quad to single
FMOVs	fmovs	freg , freg	Move
FNEGs		rs2...rd
	fnegs	freg , freg	Negate
FABSs		rs2...rd
	fabss	freg , freg rs2...rd	Absolute value

* Types of Operands are denoted by the following lower-case letters: i integer
s	single
d	double
q	quad

Table 5-4 (Continued)

SPARC	* Mnemonic	Argument List	Description
FSQRTs	fsqrts	freg , freg	Square root
FSQRTd		rs2...rd
	fsqrtd	freg , freg
FSQRTq		rs2...rd
	fsqrtq	freg , freg rs2...rd
FADDs	fadds	freg , freg , freg	Add
FADDd		rs1...rs2...rd
	faddd	freg , freg , freg
FADDq		rs1...rs2...rd
	faddq	freg , freg , freg rs1...rs2...rd
FSUBs	fsubs	freg , freg , freg	Subtract
FSUBd		rs1...rs2...rd
	fsubd	freg , freg , freg
FSUBq		rs1...rs2...rd
	fsubx	freg , freg , freg rs1...rs2...rd
FMULs	fmuls	freg , freg , freg	Multiply
FMULd		rs1...rs2...rd
	fmuld	freg , freg , freg
FMULq		rs1...rs2...rd
	fmulq	freg , freg , freg rs1...rs2...rd
FdMULq	fmulq	freg , freg , freg	Multiply double to quad
FsMULd		rs1...rs2...rd
	fsmuld	freg , freg , freg rs1...rs2...rd	Multiply single to double
FDIVs	fdivs	freg , freg , freg	Divide
FDIVd		rs1...rs2...rd
	fdivd	freg , freg , freg
FDIVq		rs1...rs2...rd
	fdivq	freg , freg , freg rs1...rs2...rd

* Types of Operands are denoted by the following lower-case letters: i integer
s	single
d	double
q	quad

Table 5-4 (Continued)

SPARC	* Mnemonic	Argument List	Description
FCMPs	fcmps	freg , freg	Compare
FCMPd		rs1...rs2
	fcmpd	freg , freg
FCMPq		rs1...rs2
	fcmpq	freg , freg
FCMPEs		rs1...rs2
	fcmpes	freg , freg	Compare, generate exception
FCMPEd		rs1...rs2	if not ordered
	fcmped	freg , freg
FCMPEq		rs1...rs2
	fcmpeq	freg , freg rs1...rs2

* Types of Operands are denoted by the following lower-case letters: i integer
s	single
d	double
q	quad

Coprocessor Instructions

All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. The data types supported by the coprocessor are coprocessor-dependent. Operand alignment is also coprocessor-dependent. Coprocessor-operate instructions are described in Table 5-5.

If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0, or if a coprocessor is not present, a cpopn instruction causes a cp_disabled trap.

The conditions that cause a cp_exception trap are coprocessor-dependent.

Table 5-5

SPARC	Mnemonic	Argument List	Name	Comments
CPop1	cpop1	opc, reg , rs1 reg , reg rs2..rd	Coprocessor operation
CPop2	cpop2	opc, reg , rs1 reg , reg rs2..rd	Coprocessor operation	May modify ccc

Synthetic Instructions

Table 5-6 describes the mapping of synthetic instructions to hardware instructions.

Table 5-6

Synthetic Instruction		Hardware Equivalent(s)		Comment
btst	reg_or_imm, reg	andcc	reg , reg_or_imm, %g0	Bit test
bset	rs1 reg_or_imm, reg	or	rs1 reg , reg_or_imm, reg rd.........rd	Bit set
bclr	rd reg_or_imm, reg	andn	reg , reg_or_imm, reg rd.........rd	Bit clear
	rd		reg , reg_or_imm, reg rd.........rd
btog	reg_or_imm, regrd	xor		Bit toggle
call	reg_or_imm	jmpl	reg_or_imm, %o7
clr	reg	or	%g0, %g0, reg	Clear (zero)
clrb	rd [address]	stb	rd %g0, [address]	register Clear byte
clrh	[address]	sth	%g0, [address]	Clear halfword
clr	[address]	st	%g0, [address]	Clear word
cmp	reg, reg_or_imm	subcc	reg , reg_or_imm, %g0 rs1	Compare

Table 5-6 (Continued)

Synthetic Instruction		Hardware Equivalent(s)		Comment
dec	reg	sub	reg , 1, reg	Decrement by 1
dec	rd const13, reg	sub	rd....rd reg , const13, reg	Decrement by
	rd		rd.........rd	const13
deccc	reg	subcc	reg , 1, reg
deccc	rd const13, regrd	subcc	rd....rd reg , const13, reg rd........rd	Decrement by 1 and set icc Decrement by const13 and set icc
dec	reg	sub	reg , 1, reg	Decrement by 1
dec	rd const13, reg	sub	rd....rd reg , const13, reg	Decrement by
	rd		rd.........rd	const13
deccc	reg	subcc	reg , 1, reg
deccc	rd const13, regrd	subcc	rd....rd reg , const13, reg rd........rd	Decrement by 1 and set icc Decrement by const13 and set icc
inc	reg	add	reg , 1, reg	Increment by 1
inc	rd const13, reg	add	rd....rd reg , const13, reg	Increment by
	rd		rd........rd	const13
inccc	reg	addcc	reg , 1, reg
inccc	rd const13, regrd	addcc	rd....rd reg , const13, reg rd........rd	Increment by 1 and set icc Increment by const13 and set icc
jmp	address	jmpl	address, %g0

Table 5-6 (Continued)

Synthetic Instruction		Hardware Equivalent(s)		Comment
mov	reg_or_imm,reg	or	%g0, reg_or_imm, reg
mov	rd %y, reg	rd	rd %y, reg
mov	rs1 %psr, reg	rd	rs1 %psr, reg
mov	rs1 %wim, reg	rd	rs1 %wim, reg
mov	rs1 %tbr, reg	rd	rs1 %tbr, reg
mov	rs1 reg_or_imm, %y	wr	rs1 %g0,reg_or_imm,%y
mov	reg_or_imm, %psr	wr	%g0,reg_or_imm,%psr
mov	reg_or_imm, %wim	wr	%g0,reg_or_imm,%wim
mov	reg_or_imm, %tbr	wr	%g0,reg_or_imm,%tbr
not	reg , reg	xnor	reg , %g0, reg	one's complement
not	rs1..rd reg	xnor	rs1......rd reg , %g0, reg	one's complement
neg	rd reg , reg	sub	rd......rd %g0, reg , reg	two's complement
neg	rs1..rd reg	sub	rs2..rd %g0, reg , reg	two's complement
	rd		rd..rd
restore		restore	%g0, %g0, %g0	trivial restore
ret		jmpl	%i7+8, %g0	return from
retl		jmpl	%o7+8, %g0	subroutine return from leaf subroutine
save		save	%g0, %g0, %g0	trivial save Warning - trivial save should only be used in supervisor code!

Table 5-6 (Continued)

Synthetic Instruction		Hardware Equivalent(s)		Comment
set	value,reg	or	%g0, value, reg	if -4096 . value . 4095
	rd		rd	if ((value & 0x3ff) == 0)
set	value,reg	sethi	%hi(value), reg
	rd		rd	otherwise
set	value,regrd	sethi	%hi(value), reg ; rd
		or	reg , %lo(value), reg rd..........rd	Warning - Do not use the set synthetic instruction in an instruction delay slot.
skipz		bnz,a .+8		if z is set, ignores
skipnz		bz,a .+8		next instruction if z is not set, ignores next instruction
tst	reg	orcc	reg , %g0, %g0 rs1	test